max9214eumtd Maxim Integrated Products, Inc., max9214eumtd Datasheet - Page 11

• Manufacturer Part Number: max9214eumtd
• Description: Programmable Dc-balance 21-bit Deserializers
• Manufacturer: Maxim Integrated Products, Inc.

The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (R
output resistor (R
itors (C). The RC time constant for two equal-value
series capacitors is (C x (R
RC time constant for four equal-value series capacitors
is (C x (R
R
ance (usually 100Ω) and R
driver design (the minimum differential output resis-
tance of 78Ω for the MAX9209/MAX9211/MAX9213/
MAX9215 serializers is used in the following example).
This leaves the capacitor selection to change the sys-
tem time constant.
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
where:
C = AC-coupling capacitor (F).
t
Figure 12. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
B
T
= bit time (s).
C = - (2 x t
is required to match the transmission line imped-
T
+ R
PWRDWN
TxCLK IN
B
TxIN
O
x DSV) / (ln (1 - D) x (R
))/4 (Figure 13).
O
______________________________________________________________________________________
), and the series AC-coupling capac-
7
7
7
(7 + 2):1
(7 + 2):1
(7 + 2):1
O
PLL
T
is determined by the LVDS
+ R
21:3 SERIALIZER
MAX9209
MAX9211
MAX9213
MAX9215
O
))/2 (Figure 12). The
T
), the LVDS driver
T
+ R
O
)) (Eq 1)
SERIALIZER INSTEAD OF THE DESERIALIZER.
TxOUT
TxCLK OUT
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT THE
HIGH-FREQUENCY, CERAMIC
Programmable DC-Balance
DSV = digital sum variation (integer).
ln = natural log.
D = droop (% of signal amplitude).
R
R
Equation 1 is for two series capacitors (Figure 12). The
bit time (t
9. The DSV is 10. See equation 3 for four series capaci-
tors (Figure 13).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
Jitter due to droop is proportional to the droop and
transition time:
where:
t
J
T
O
C = - (2 x t
C = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100Ω + 78Ω))
C = 0.0773µF
= jitter (s).
= termination resistor (Ω).
100Ω
100Ω
100Ω
100Ω
= output resistance (Ω).
RxCLK IN
RxIN
21-Bit Deserializers
B
) is the period of the parallel clock divided by
B
x DSV) / (ln (1 - D) x (R
3:21 DESERIALIZER
MAX9210
MAX9212
MAX9214
MAX9216
MAX9220
MAX9222
t
J
= t
T
x D (Eq 2)
1:(9 - 2)
1:(9 - 2)
1:(9 - 2)
PLL
T
7
7
7
+ R
RxOUT
PWRDWN
RxCLK OUT
O
))
11