max9126euet Maxim Integrated Products, Inc., max9126euet Datasheet

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max9126euet

Manufacturer Part Number
max9126euet
Description
Quad Lvds Line Receivers With Integrated Termination
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
The MAX9125/MAX9126 quad low-voltage differential
signaling (LVDS) line receivers are ideal for applica-
tions requiring high data rates, low power, and reduced
noise. The MAX9125/MAX9126 are guaranteed to
receive data at speeds up to 500Mbps (250MHz) over
controlled-impedance media of approximately 100Ω.
The transmission media may be printed circuit (PC)
board traces or cables.
The MAX9125/MAX9126 accept four LVDS differential
inputs and translate them to 3.3V CMOS outputs. The
MAX9126 features integrated parallel termination resis-
tors (nominally 115Ω), which eliminate the requirement
for four discrete termination resistors and reduce stub
length. The MAX9125 inputs are high impedance and
require an external termination resistor when used in a
point-to-point connection.
The devices support a wide common-mode input range
of 0.05V to 2.35V, allowing for ground potential differ-
ences and common-mode noise between the driver
and the receiver. A fail-safe feature sets the output high
when the inputs are open, or when the inputs are
undriven and shorted or parallel terminated. The EN
and EN inputs control the high-impedance output and
are common to all four receivers. Inputs conform to the
ANSI TIA/EIA-644 LVDS standard. The MAX9125/
MAX9126 operate from a single +3.3V supply, are
specified for operation from -40°C to +85°C, and are
available in 16-pin TSSOP and SO packages. Refer to
the MAX9124 data sheet for a quad LVDS line driver.
19-1908; Rev 0; 5/01
Pin Configuration appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Digital Copiers
Laser Printers
Cellular Phone Base Stations
Add/Drop Muxes
Digital Cross-Connects
DSLAMs
Network Switches/Routers
Backplane Interconnect
Clock Distribution
________________________________________________________________ Maxim Integrated Products
General Description
Applications
Quad LVDS Line Receivers with
Integrated Termination
o Integrated Termination Eliminates Four External
o Pin Compatible with DS90LV032A
o Guaranteed 500Mbps Data Rate
o 300ps Pulse Skew (max)
o Conform to ANSI TIA/EIA-644 LVDS Standard
o Single +3.3V Supply
o Low 70µA Shutdown Supply Current
o Fail-Safe Circuit
LVTTL/LVCMOS
Resistors (MAX9126)
DATA INPUT
MAX9125EUE
MAX9126EUE
MAX9125ESE
MAX9126ESE
PART
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
MAX9124
Typical Application Circuit
T
T
T
T
X
X
X
X
LVDS SIGNALS
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Ordering Information
115Ω
115Ω
115Ω
115Ω
MAX9126
R
R
R
R
PIN-PACKAGE
16 TSSOP
16 SO
16 TSSOP
16 SO
X
X
X
X
Features
LVTTL/LVCMOS
DATA OUTPUT
1

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max9126euet Summary of contents

Page 1

Rev 0; 5/01 General Description The MAX9125/MAX9126 quad low-voltage differential signaling (LVDS) line receivers are ideal for applica- tions requiring high data rates, low power, and reduced noise. The MAX9125/MAX9126 are guaranteed to receive data at speeds up to ...

Page 2

Quad LVDS Line Receivers with Integrated Termination ABSOLUTE MAXIMUM RATINGS V to GND ...........................................................-0.3V to +4.0V CC IN_+, IN_- to GND .................................................-0.3V to +4.0V EN GND ...........................................-0. OUT_ to GND .............................................-0. Continuous Power Dissipation ...

Page 3

DC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V, differential input voltage CC -40°C to +85°C. Typical values are at V PARAMETER SYMBOL LOGIC INPUTS (EN, EN) Input High Voltage Input Low Voltage Input Current SUPPLY Supply Current Disabled Supply ...

Page 4

Quad LVDS Line Receivers with Integrated Termination AC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V 10pF, differential input voltage input rise and fall time = 1ns (20% to 80%), input ...

Page 5

V = 200mV +1.2V DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE 2.6 2.5 t PHLD 2.4 2.3 t PLHD 2.2 0 0.5 1.0 1.5 2.0 COMMON-MODE VOLTAGE (V) PULSE SKEW ...

Page 6

Quad LVDS Line Receivers with Integrated Termination Table 1. Input/Output Function Table ENABLES EN L All other combinations of ENABLE inputs IN2 V - 0.3V CC IN_+ R IN1 R IN1 IN_- MAX9125 Figure 1. Inputs with ...

Page 7

Figure 2. Transition Time and Propagation Delay Test Circuit IN_- IN_ _+) IN_ IN NOTE OUT_ Figure 3. Transition Time and Propagation Delay Timing Diagram GENERATOR ...

Page 8

Quad LVDS Line Receivers with Integrated Termination EN WHEN 1.5V 1.5V EN WHEN EN = GND t PLZ OUTPUT WHEN V = -100mV ID t PHZ OUTPUT WHEN V = +100mV ID Figure 5. High-Z Delay ...

Page 9

Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to ...

Page 10

Quad LVDS Line Receivers with Integrated Termination Pin Configuration TOP VIEW IN1- 1 IN1+ 2 OUT1 3 MAX9125 ...

Page 11

Quad LVDS Line Receivers with ______________________________________________________________________________________ Integrated Termination Package Information 11 ...

Page 12

Quad LVDS Line Receivers with Integrated Termination Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are Maxim cannot assume responsibility for use of any circuitry other ...

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