max9122euet Maxim Integrated Products, Inc., max9122euet Datasheet
max9122euet
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max9122euet Summary of contents
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Rev 0; 6/01 Integrated Termination and Flow-Through Pinout General Description The MAX9121/MAX9122 quad low-voltage differential sig- naling (LVDS) differential line receivers are ideal for appli- cations requiring high data rates, low power, and low noise. The MAX9121/MAX9122 are guaranteed ...
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout ABSOLUTE MAXIMUM RATINGS V to GND ...........................................................-0.3V to +4.0V CC IN_+, IN_- to GND .................................................-0.3V to +4.0V EN GND ...........................................-0. OUT_ to GND .............................................-0. ...
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Integrated Termination and Flow-Through Pinout DC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V, differential input voltage | -40°C to +85°C. Typical values are PARAMETER SYMBOL LOGIC INPUTS (EN, EN) Input High Voltage Input ...
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout AC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V 15pF, differential input voltage | /2|, input rise and fall time = 1ns (20% to 80%), ...
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Integrated Termination and Flow-Through Pinout (V = +3.3V +1.2V 0.2V OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE 100 3.0 3.3 SUPPLY VOLTAGE (V) DIFFERENTIAL ...
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout PIN NAME IN_- Inverting Differential Receiver Inputs IN_+ Noninverting Differential Receiver Inputs Receiver Enable Inputs. When EN = high and EN = ...
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Integrated Termination and Flow-Through Pinout IN2 V - 0.3V CC IN_+ R IN1 R IN1 IN_- MAX9121 Figure 1. Input with Fail-Safe Network received. Open or undriven terminated input conditions can occur when a cable is disconnected ...
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout GENERATOR** Figure 2. Propagation Delay and Transition Time Test Circuit IN_- IN_ IN_+ IN_- NOTE ...
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Integrated Termination and Flow-Through Pinout Figure 4. High-Impedance Delay Test Circuit EN WHEN EN = GND OR OPEN EN WHEN OUTPUT WHEN V = -100mV ID OUTPUT WHEN V = +100mV ID Figure 5. High-Impedance Delay ...
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout IN1+ IN1- IN2+ IN2- IN3+ IN3- IN4+ IN4 TOP VIEW 10 ______________________________________________________________________________________ V CC IN1+ OUT1 107Ω IN1- IN2+ OUT2 107Ω IN2- IN3+ OUT3 107Ω IN3- IN4+ OUT4 ...
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Integrated Termination and Flow-Through Pinout ______________________________________________________________________________________ Quad LVDS Line Receivers with Package Information 11 ...
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change ...