max9179euet Maxim Integrated Products, Inc., max9179euet Datasheet

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max9179euet

Manufacturer Part Number
max9179euet
Description
Max9179 Quad Lvds Receiver With Hysteresis
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
The MAX9179 is a quad low-voltage differential
signaling (LVDS) line receiver designed for applications
requiring high data rates, low power dissipation, and
noise immunity. The receiver accepts four LVDS input
signals and translates them to 3.3V LVCMOS output lev-
els at speeds up to 400Mbps. The receiver features
built-in hysteresis, which improves noise immunity and
prevents multiple switching on slow transitioning inputs.
The device supports a wide 0.038V to 2.362V common-
mode input voltage range, allowing for ground potential
differences and common-mode noise between the driver
and the receiver. A fail-safe circuit sets the output high
when the input is open, undriven and shorted, or undriven
and terminated. Common enable inputs control the high-
impedance outputs.
The MAX9179 has a flow-through pinout for easy PC
board layout, and is pin compatible with the MAX9121
and the DS90LV048A with the additional features of
high ESD tolerance and built-in hysteresis.
The MAX9179 operates from a single 3.3V supply, and is
specified for operation from -40°C to +85°C. The device
is offered in 16-pin TSSOP and thin QFN packages.
19-2752; Rev 0; 2/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Laser Printers
Digital Copiers
Cell-Phone Base Stations
Telecom Switching Equipment
LCD Displays
Network Switches/Routers
Backplane Interconnect
Clock Distribution
________________________________________________________________ Maxim Integrated Products
TOP VIEW
General Description
Quad LVDS Receiver with Hysteresis
IN1+
IN2+
IN3+
IN4+
IN1-
IN2-
IN3-
IN4-
1
2
6
3
4
5
7
8
Applications
MAX9179
TSSOP
16
15
14
13
12
11
10
9
EN
OUT1
OUT2
V
GND
OUT3
OUT4
EN
CC
IN2+
IN3+
IN2-
IN3-
o Guaranteed 400Mbps Data Rate
o 50mV (typ) Hysteresis
o Overshoot/Undershoot Protection (-1.0V or V
o IEC61000-4-2 Level 4 ESD Tolerance
o AC Specifications Guaranteed with |V
o Single 3.3V Supply
o Fail-Safe Circuit
o Flow-Through Pinout
o Low-Power CMOS Design
o Conforms to ANSI TIA/EIA-644 LVDS Standard
o High-Impedance Inputs when Powered Off
o Pin Compatible with the MAX9121 and the
o Small Thin QFN Package Available
*Future product—contact factory for availability.
**EP = Exposed paddle.
Functional Diagram appears at end of data sheet.
(LEADS UNDER PACKAGE)
MAX9179EUE
MAX9179ETE*
1.0V) on Enables
DS90LV048A
1
2
3
4
Simplifies PC Board Layout
Reduces Crosstalk
IN1+
IN4+
16
5
PART
THIN QFN
EXPOSED PAD
MAX9179
IN1-
IN4-
15
6
EN
EN
14
7
OUT1
OUT4
13
8
12
11
10
9
-40°C to +85°C
-40°C to +85°C
Ordering Information
TEMP RANGE
OUT2
V
GND
OUT3
CC
Pin Configurations
PIN-PACKAGE
16 TSSOP
16 Thin QFN-EP**
Features
ID
|
=
100mV
CC
+
1

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max9179euet Summary of contents

Page 1

Rev 0; 2/03 Quad LVDS Receiver with Hysteresis General Description The MAX9179 is a quad low-voltage differential signaling (LVDS) line receiver designed for applications requiring high data rates, low power dissipation, and noise immunity. The receiver accepts four LVDS ...

Page 2

Quad LVDS Receiver with Hysteresis ABSOLUTE MAXIMUM RATINGS V to GND ...........................................................-0.3V to +4.0V CC IN_+, IN_- to GND .................................................-0.3V to +4.0V EN GND ...........................................-1. OUT_ to GND .............................................-0. Continuous Power Dissipation (T = ...

Page 3

Quad LVDS Receiver with Hysteresis AC ELECTRICAL CHARACTERISTICS (V = 3.0V to 3.6V 15pF, differential input voltage | -40°C to +85°C, unless otherwise noted. Typical values are PARAMETER SYMBOL Differential Propagation ...

Page 4

Quad LVDS Receiver with Hysteresis V OUT HYSTERESIS Figure 1. Input Thresholds and Hysteresis IN2 IN_ 0. IN1 R IN1 IN_- Figure 2. Fail-Safe Input Circuit IN_+ ...

Page 5

Quad LVDS Receiver with Hysteresis (V = 3.3V 1.2V 0.15V SUPPLY CURRENT vs. FREQUENCY 110 ALL CHANNELS DRIVEN 100 150 200 250 300 FREQUENCY ...

Page 6

Quad LVDS Receiver with Hysteresis (V = 3.3V 1.2V 0.15V DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE 3.4 3.2 3.0 2.8 t PHLD 2.6 t PLHD 2.4 2.2 2.0 -40 - ...

Page 7

Quad LVDS Receiver with Hysteresis PIN NAME TSSOP QFN 1 15 IN1- Inverting LVDS Input IN1+ Noninverting LVDS Input IN2+ Noninverting LVDS Input IN2- Inverting LVDS Input IN3- ...

Page 8

Quad LVDS Receiver with Hysteresis Table 1. Functional Table ENABLES INPUTS EN EN (IN_+) - (IN_-) ≥ +75mV ≤ -75mV open Open, undriven short, or undriven terminated All other combinations X of enable inputs H = High ...

Page 9

Quad LVDS Receiver with Hysteresis Cables and Connectors Interconnect for LVDS typically has a controlled differ- ential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbal- anced cables ...

Page 10

Quad LVDS Receiver with Hysteresis (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) 10 ______________________________________________________________________________________ Package Information ...

Page 11

Quad LVDS Receiver with Hysteresis (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry ...

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