max9761 Maxim Integrated Products, Inc., max9761 Datasheet - Page 15

• Manufacturer Part Number: max9761
• Description: Stereo 3w Audio Power Amplifiers With Headphone Drive And Input Mux
• Manufacturer: Maxim Integrated Products, Inc.

The clickless power-down cycle only occurs when the
device is in headphone mode. The speaker mode is
inherently clickless, the differential architecture cancels
the DC shift across the speaker. The MAX9760–
MAX9763 BTL outputs are pulled to GND quickly and
simultaneously, resulting in no audible components. If
the MAX9760–MAX9763 are only used as speaker
amplifiers, then reservoir capacitors or secondary sup-
plies are not necessary.
When using a reservoir capacitor, a 220µF capacitor
provides optimum charge storage for the shutdown
cycle for all conditions. If a smaller reservoir capacitor
is desired, decrease the size of C
causes the output DC level to decay at a faster rate,
increasing the audible content at the speaker, but
reducing the duration of the shutdown cycle.
The MAX9760/MAX9762 feature an I
ible 2-wire serial interface consisting of a serial data
line (SDA) and a serial clock line (SCL). SDA and SCL
facilitate bidirectional communication between the
MAX9760/MAX9762 and the master at clock rates up to
400kHz. Figure 3 shows the 2-wire interface timing dia-
gram. The MAX9760/MAX9762 are transmit/receive
slave-only devices, relying upon a master to generate a
clock signal. The master (typically a microcontroller) ini-
tiates data transfer on the bus and generates SCL to
permit that transfer.
A master device communicates to the MAX9760/
MAX9762 by transmitting the proper address followed
by a command and/or data words. Each transmit
sequence is framed by a START (S) or REPEATED
START (S
word transmitted over the bus is 8 bits long and is
always followed by an acknowledge clock pulse.
Figure 3. 2-Wire Serial Interface Timing Diagram
SDA
SCL
r
) condition and a STOP (P) condition. Each
t
HD, STA
CONDITION
START
______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
t
LOW
t
R
t
t
SU, DAT
HIGH
BIAS
Digital Interface
2
C/SMBus-compat-
t
F
. A smaller C
Headphone Drive and Input Mux
t
HD, DAT
BIAS
t
HD, STA
The MAX9760/MAX9762 SDA and SCL amplifiers are
open-drain outputs requiring a pullup resistor (500Ω or
greater) to generate a logic high voltage. Series resis-
tors in line with SDA and SCL are optional. These series
resistors protect the input stages of the devices from
high-voltage spikes on the bus lines, and minimize
crosstalk and undershoot of the bus signals.
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see START and
STOP Conditions section). SDA and SCL idle high
when the I
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure 4). A START condition from the master signals
the beginning of a transmission to the MAX9760/
Figure 4. START/STOP Conditions
CONDITION
REPEATED
START
SDA
SCL
t
HD, STA
2
S
C bus is not busy.
t
SP
START and STOP Conditions
t
SU, STO
Sr
CONDITION
STOP
t
BUF
CONDITION
START
Bit Transfer
P
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