max9702etit Maxim Integrated Products, Inc., max9702etit Datasheet - Page 21

• Manufacturer Part Number: max9702etit
• Description: Max9702 1.8w, Filterless, Stereo, Class D Audio Power Amplifier And Directdrive Stereo Headphone Amplifier
• Manufacturer: Maxim Integrated Products, Inc.

The MAX9702 features an I
consisting of a serial data line (SDA) and a serial clock
line (SCL). SDA and SCL facilitate communication
between the MAX9702 and the master at clock rates up
to 400kHz. Figure 9 shows the 2-wire interface timing
diagram. The MAX9702 is a receive-only slave device
relying on the master to generate the SCL signal. The
MAX9702 cannot write to the SDA bus except to
acknowledge the receipt of data from the master. The
MAX9702 does not acknowledge a read command
from the master. The master, typically a microcontroller,
generates SCL and initiates data transfer on the bus.
A master device communicates to the MAX9702 by
transmitting the proper address followed by the data
word. Each transmit sequence is framed by a START (S)
or REPEATED START (S
Amplifier and DirectDrive Stereo Headphone Amplifier
Figure 9. 2-Wire Serial-Interface Timing Diagram
Figure 10. START, STOP, and REPEATED START Conditions
SDA
SCL
SDA
SCL
t
HD, STA
S
CONDITION
START
______________________________________________________________________________________
1.8W, Filterless, Stereo, Class D Audio Power
t
LOW
r
) condition and a STOP (P) con-
t
R
Sr
2
t
t
C 2-wire serial interface
SU, DAT
HIGH
t
F
I
2
t
HD, DAT
C Interface
P
t
SU, STA
dition. Each word transmitted over the bus is 8 bits long
and is always followed by an acknowledge clock pulse.
The MAX9702 SDA line operates as both an input and
an open-drain output. A pullup resistor, greater than
500Ω, is required on the SDA bus. The MAX9702 SCL
line operates as an input only. A pullup resistor, greater
than 500Ω, is required on SCL if there are multiple mas-
ters on the bus, or if the master in a single-master sys-
tem has an open-drain SCL output. Series resistors in
line with SDA and SCL are optional. Series resistors
protect the digital inputs of the MAX9702 from high-
voltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP Conditions
section). SDA and SCL idle high when the I
not busy.
A master device initiates communication by issuing a
START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is a
low-to-high transition on SDA while SCL is high (Figure
10). A START (S) condition from the master signals the
beginning of a transmission to the MAX9702. The mas-
ter terminates transmission and frees the bus by issu-
ing a STOP (P) condition. The bus remains active if a
REPEATED START (Sr) condition is generated instead
of a STOP condition.
CONDITION
REPEATED
START
t
HD, STA
t
SP
START and STOP Conditions
t
SU, STO
CONDITION
STOP
t
BUF
Bit Transfer
CONDITION
2
START
C bus is
21