max9726aetpt Maxim Integrated Products, Inc., max9726aetpt Datasheet - Page 12
max9726aetpt
Manufacturer Part Number
max9726aetpt
Description
Max9726 Directdrive, Headphone Amplifier With Bassmax, I?c, Volume And Gain Control
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.MAX9726AETPT.pdf
(24 pages)
The MAX9726 includes a 64-level volume control that
adjusts the gain of the output amplifiers according to
the code contained in the command register. Volume is
programmed through the command register bits [5:0].
Table 5 shows all possible attenuation settings of the
MAX9726 with respect to the overall gain set by the
external gain-setting resistors (R
uation is typically better than 120dB when driving a
32Ω load. To perform smooth-sounding volume
changes, step through all intermediate volume settings
at a rate of approximately 2ms per step when a volume
change occurs.
The MAX9726 features an I
2-wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate communication between the MAX9726 and the
master at clock rates up to 400kHz. Figure 3 shows the
2-wire interface timing diagram. The MAX9726 is a
receive-only slave device relying on the master to gen-
erate the SCL signal. The MAX9726 cannot write to the
DirectDrive, Headphone Amplifier with
BassMax, I
Figure 3. 2-Wire Serial-Interface Timing Diagram
12
SDA
SCL
______________________________________________________________________________________
t
HD, STA
CONDITION
START
t
LOW
2
t
R
C, Volume and Gain Control
t
t
SU, DAT
HIGH
2
C-/SMBus-compatible,
IN
t
and R
F
Serial Interface
Volume Control
t
HD, DAT
F
). Mute atten-
t
SU, STA
SDA bus except to acknowledge the receipt of data
from the master. The master, typically a microcontroller,
generates SCL and initiates data transfer on the bus.
A master device communicates to the MAX9726 by
transmitting the slave address with the read/write (R/W)
bit followed by the data word. Each transmit sequence
is framed by a START (S) or REPEATED START (Sr)
condition and a STOP (P) condition. Each word trans-
mitted over the bus is 8 bits long and is always followed
by an acknowledge clock pulse.
The MAX9726 SDA line operates as both an input and
an open-drain output. A pullup resistor, greater than
500Ω, is required on the SDA bus. The MAX9726 SCL
line operates as an input only. A pullup resistor, greater
than 500Ω, is required on SCL if there are multiple mas-
ters on the bus, or if the master in a single-master sys-
tem has an open-drain SCL output. Series resistors in
line with SDA and SCL are optional. Series resistors
protect the digital inputs of the MAX9726 from high-
voltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
CONDITION
REPEATED
START
t
HD, STA
t
SP
t
SU, STO
CONDITION
STOP
t
BUF
CONDITION
START