nb3n65027 ON Semiconductor, nb3n65027 Datasheet

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nb3n65027

Manufacturer Part Number
nb3n65027
Description
3.3v Programmable 3-pll Clock Synthesizer With 6 Lvttl/lvcmos Outputs W/oe
Manufacturer
ON Semiconductor
Datasheet

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NB3N65027
3.3V Programmable 3-PLL Clock
Synthesizer with
6 LVTTL/LVCMOS Outputs w/OE
It accepts a 10 MHz to 27 MHz clock or fundamental mode crystal as
the reference source and drives three independent, low noise
phase−locked loops (PLLs).
bank output frequencies. ACS1 and BCS1 are two−level
LVTTL/LVCMOS inputs, High and Low. ACS0, BCS0 and CCS are
three−level LVCMOS inputs, High, Mid and Low.
banks of two outputs each. Banks A and B offer a 1X and a 1/2X
output. Using a 25 MHz crystal, the selectable output frequencies
range from 16 2/3 MHz to 133 1/3 MHz. A 12.5 MHz crystal offers
from 8 1/3 MHz to 66 2/3 MHz. In addition, the NB3N65027 will
generate a buffered reference LVTTL/LVCMOS output, REFOUT,
10 MHz to 27 MHz. See Tables 2 through 9 for the variety of available
output frequencies. The OE pin, when set LOW, will disable the output
drivers to high impedance.
operating temperature range from −40°C to +85°C, and is offered in a
QSOP−20 RoHS compliant package.
flexibility, and high performance for Network, PCI and SDRAM
applications.
Features
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 2
The NB3N65027 is a LVCMOS PLL−synthesized clock generator.
Control lines ACSx, BCSx and CCS will select their appropriate
The NB3N65027 has three independent LVTTL/LVCMOS output
The NB3N65027 operates from a single +3.3 V supply across the
The NB3N65027 provides the optimum combination of low cost,
12.5 MHz or 25 MHz Fundamental Crystal or Clock
Input
Six Output Clocks with Selectable Frequencies
Buffered Crystal Reference Output
SDRAM Frequencies of 67, 83, 100, and 133 MHz
LVCMOS with 25 mA Output Drive Capability at TTL
Levels
25 or 12.5 MHz
crystal or clock
ACS1
ACS0
BCS1
BCS0
CCS
X2
X1/ICLK
C
LX2
C
LX1
Figure 1. Simplified Logic Diagram
Oscillator
Buffer /
1
Operating Range: V
QSOP−20 Package, 150 mil
−40°C to +85°C Ambient Operating Temperature
These Devices are Pb−Free and are RoHS Compliant
and Control
Synthesis
Circuitry
PLLA
PLLB
PLLC
Clock
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
VDD
GND
CASE 492AC
QSOP20
3N65027 = Specific Device Code
A
WL
Y
WW
G
ORDERING INFORMATION
CC
B2
B2
http://onsemi.com
OE (all outputs)
= 3.3 V ±10%
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
MARKING DIAGRAM
Publication Order Number:
AWLYWWG
3N65027
NB3N65027/D
CLKA1
CLKA2
CLKB1
CLKB2
CLKC1
CLKC2
REFOUT

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nb3n65027 Summary of contents

Page 1

... Using a 25 MHz crystal, the selectable output frequencies range from 16 2/3 MHz to 133 1/3 MHz. A 12.5 MHz crystal offers from 8 1/3 MHz to 66 2/3 MHz. In addition, the NB3N65027 will generate a buffered reference LVTTL/LVCMOS output, REFOUT, 10 MHz to 27 MHz. See Tables 2 through 9 for the variety of available output frequencies ...

Page 2

Table 1. PIN DESCRIPTION (Note 1) Pin Number Pin Name Pin Type 1 ACS0 Tri−Level Input 2 X2 Input 3 X1/ICLK Input 4 VDD Power 5 ACS1 Two−Level Input 6 GND Power 7 CLKC1 Output 8 CLKC2 Output 9 CLKB2 ...

Page 3

FOR A 25 MHz FUNDAMENTAL CRYSTAL OR CLOCK INPUT, THE FOLLOWING FOUR TABLES APPLY: Table 2. A CLOCKS SELECT TABLE (outputs in MHz) ACS1 ACS0 CLKA1 0 0 100 0 M Test 33.3333 1 M ...

Page 4

Table 10. ATTRIBUTES ESD Protection R − Internal Input Pull−up Resistor PU Z − Nominal Output Impedance OUT Moisture Sensitivity (Note 2) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see ...

Page 5

Table 12. DC CHARACTERISTICS Symbol Characteristic POWER SUPPLY V Power Supply Voltage; GND = Power Supply Current for OUTPUTS V Output HIGH Voltage 3. Output LOW Voltage; OL ...

Page 6

... External Components The NB3N65027 requires a minimum number of external components for proper operation. Decoupling Capacitor Decoupling capacitors of 0.01 mF must be connected between each V and GND (pins 4 and 6, pins 16 and 14 close to the device as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB ...

Page 7

... BSC 8.66 BSC E 0.236 BSC 5.99 BSC E1 0.154 BSC 3.91 BSC e 0.025 BSC 0.635 BSC h 0.010 0.020 0.25 L 0.016 0.050 0.41 L2 0.010 BSC 0.25 BSC 20X 1.12 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB3N65027/D 1.75 0.25 0.30 0.25 0.51 1. ...

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