nb3n2302 ON Semiconductor, nb3n2302 Datasheet

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nb3n2302

Manufacturer Part Number
nb3n2302
Description
3.3v / 5v 5mhz To 133mhz Frequency Multiplier And Zero Delay Buffer
Manufacturer
ON Semiconductor
Datasheet
NB3N2302
3.3V / 5V 5MHz to 133MHz
Frequency Multiplier and
Zero Delay Buffer
Description
5 MHz to 133 MHz with a 3.3 V or 5 V power supply. It accepts a
reference input and drives a B1 and a B2 clock output. The
NB3N2302 has an on−chip PLL which locks to the input reference
clock presented on the REF_IN pin. The PLL feedback is required to
be driven to the FBIN pin and can be obtained by connecting either the
OUT1 or OUT2 pin to the FBIN pin.
frequency combinations as shown in Table 1.
Features
© Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 1
The NB3N2302 is a versatile Zero Delay Buffer that operates from
The Function Select inputs control the various multiplier output
for Options
Output Frequency Range: 5 MHz to 133 MHz
Two LVTTL/LVCMOS Outputs
65 ps Typical Jitter OUT2
115 ps Typical Jitter OUT1
25 ps Typical Output−to−Output Skew
Operating Voltage Range: V
Clock Multiplication of the Reference Input Frequency, See Table 1
Packaged in 8−Pin SOIC
−40°C to +85°C Ambient Operating Temperature Range
Ideal for PCI−X and Networking Clocks
These are Pb−Free Devices
REF_IN
FS0
FS1
DD
= 3.3 V $5% or 5 V $10%
FBIN
Select Input
Decoding
Figure 1. Simplified Logic Diagram
PLL
1
÷2
External feedback connection
to OUT1 or OUT2, not both
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
CASE 751
D SUFFIX
8
SOIC−8
ORDERING INFORMATION
2302
A
L
Y
W
G
1
http://onsemi.com
OUT1
OUT2
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
MARKING DIAGRAM
Publication Order Number:
8
1
3N2302
ALYWG
G
NB3N2302/D

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nb3n2302 Summary of contents

Page 1

... MHz to 133 MHz with a 3 power supply. It accepts a reference input and drives a B1 and a B2 clock output. The NB3N2302 has an on−chip PLL which locks to the input reference clock presented on the REF_IN pin. The PLL feedback is required to be driven to the FBIN pin and can be obtained by connecting either the OUT1 or OUT2 pin to the FBIN pin ...

Page 2

... REF_IN Figure 2. NB3N2302 Package Pinout (Top View) 8−pin SOIC (150 mil) Table 1. CLOCK MULTIPLIER SELECT TABLE FBIN FS0 OUT1 0 OUT1 1 OUT1 0 OUT1 1 OUT2 0 OUT2 1 OUT2 0 OUT2 1 Table 2. PIN DESCRIPTION Pin Name Pin # Type 1 FBIN LVCMOS/LVTTL Input 2 REF_IN LVCMOS/LVTTL Input 3 GND Power ...

Page 3

Table 3. ATTRIBUTES ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol ...

Page 4

Table 5. DC CHARACTERISTICS V Symbol I Power Supply Current, 100 MHz, Unloaded Outputs Output HIGH Voltage I = − Output LOW Voltage Input HIGH Voltage ...

Page 5

... Overview The NB3N2302 is a two−output zero delay buffer and frequency multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero How to Implement Zero Delay Typically, Zero Delay Buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other ...

Page 6

... ORDERING INFORMATION Device NB3N2302DG NB3N2302DR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. supplied). If OUT2 is desired to be rising−edge aligned to the IN input’ ...

Page 7

... C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 J K 0.40 1.27 0.016 0.050 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 mm inches ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB3N2302/D _ ...

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