nb3n551 ON Semiconductor, nb3n551 Datasheet

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nb3n551

Manufacturer Part Number
nb3n551
Description
3.3 V / 5.0 V Ultra-low Skew 1 4 Clock Fanout Buffer
Manufacturer
ON Semiconductor
Datasheet

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NB3N551
3.3 V / 5.0 V
Ultra−Low Skew
1:4 Clock Fanout Buffer
Description
for clock distribution in mind. The NB3N551 specifically guarantees
low output−to−output skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
Features
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 2
The NB3N551 is a low skew 1−to 4 clock fanout buffer, designed
The output enable (OE) pin three−states the outputs when low.
Input/Output Clock Frequency up to 180 MHz
Low Skew Outputs (50 ps typical)
Output goes to Three−State Mode via OE
Operating Range: V
Ideal for Networking Clocks
Packaged in 8−pin SOIC
Industrial Temperature Range
These are Pb−Free Devices
CLK
Figure 1. Block Diagram
DD
= 3.0 V to 5.5 V
OE
Q1
Q2
Q3
Q4
1
†For information on tape and reel specifications,
NB3N551DG
NB3N551DR2G
NB3N551MNR4G
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
8
*For additional marking information, refer to
Device
1
Application Note AND8002/D.
(Note: Microdot may be in either location)
1
ORDERING INFORMATION
3N551 = Specific Device Code
A
L
Y
W
G
I
6K = Specific Device Code
M
G
CLK
Q1
Q2
Q3
PIN CONNECTIONS
http://onsemi.com
= Date Code
= Pb−Free Package
CASE 506AA
1
2
3
4
MN SUFFIX
CASE 751
D SUFFIX
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
SOIC−8
(Pb−Free)
(Pb−Free)
(Pb−Free)
DFN8
Package
SOIC−8
SOIC−8
DFN−8
Publication Order Number:
8
7
6
5
2500/Tape & Reel
1000/Tape & Reel
DIAGRAMS*
8
1
98 Units/Rail
MARKING
OE
V
GND
Q4
Shipping
DD
1
3N551
ALYW
NB3N551/D
G
4

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nb3n551 Summary of contents

Page 1

... Ultra−Low Skew 1:4 Clock Fanout Buffer Description The NB3N551 is a low skew 1−to 4 clock fanout buffer, designed for clock distribution in mind. The NB3N551 specifically guarantees low output−to−output skew. Optimal design, layout and processing minimize skew within a device and from device to device. ...

Page 2

PIN DESCRIPTION Pin # Name Type 1 I (LV)CMOS/(LV)TTL Input CLK 2 Q1 (LV)CMOS/(LV)TTL Output 3 Q2 (LV)CMOS/(LV)TTL Output 4 Q3 (LV)CMOS/(LV)TTL Output 5 Q4 (LV)CMOS/(LV)TTL Output 6 GND Power 7 V Power (LV)CMOS/(LV)TTL Input MAXIMUM RATINGS ...

Page 3

DC CHARACTERISTICS ( 3.6 V, GND = Symbol I Power Supply Current @ 135 MHz, No Load Output HIGH Voltage – Output LOW Voltage – I ...

Page 4

... C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004) ...

Page 5

... COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.20 0.30 D 2.00 BSC D2 1.10 1.30 E 2.00 BSC E2 0.70 0.90 e 0.50 BSC K 0.20 −−− L 0.25 0.35 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB3N551/D ...

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