nb3n3020 ON Semiconductor, nb3n3020 Datasheet - Page 2

• Manufacturer Part Number: nb3n3020
• Description: 3.3 V, Lv-pecl/lv-cmos Clock Multiplier
• Manufacturer: ON Semiconductor

2 – 210 MHz Clock
Table 1. Pin Description
5−27 MHz Crystal
1, 11, 15
8, 9, 12
7, 16
Pin
13
14
10
6
5
4
2
3
X1 / CLK
X2
or
X1/CLK
Name
CLK2
CLK2
CLK1
OE1,
GND
VDD
Sel0
Sel1
Sel2
OE2
X2
LVPECL Output
LVPECL Output
Tri−Level Input
Tri−Level Input
Tri−Level Input
Power Supply
Power Supply
Oscillator
LVCMOS
Crystal
Buffer/
Clock
LVTTL/
Output
Input
Input
Input
I/O
Select Control Block
Figure 1. NB3N3020 Simplified Logic Diagram
Sel0 Sel1 Sel2
VDD
Sca
Pre
ler
Frequency select input 0. When left open, defaults to VDD/ 2. See output select Table 2 for
details.
Frequency select input 1. When left open, defaults to VDD/ 2. See output select Table 2 for
details.
Frequency select input 2. When left open, defaults to VDD/ 2. See output select Table 2 for
details.
Positive supply voltage pins are connected to +3.3 V supply voltage.
Crystal or Clock input. Connect to 5 − 27 MHz crystal source or 2 – 210 MHz single−ended
clock. See Table 2.
Crystal input. Connect to a 5 – 27 MHz crystal or leave unconnected for clock input. See
Table 2.
Output enable input that tri−states clock outputs when low. Internal pull−up resistor to VDD.
OE1 is designated to control LV CMOS output synchronously and OE2 is designated to
control LV PECL output synchronously. See operation details in device operation.
Ground 0 V. These pins provide GND return path for the devices.
Non−inverted clock output. Clock frequency equals input frequency times multiplier.
Inverted clock output. Clock frequency equals input frequency times multiplier.
Clock Output. Clock frequency equals input frequency times multiplier.
GND
Detector
Phase
http://onsemi.com
2
Loop Filter
% N
Description
VCO
LV−CMOS/
LV−TTL
OE2
Output
OE1
Output
LV−PECL
CLK2
CLK1
CLK2