nb3n3001 ON Semiconductor, nb3n3001 Datasheet

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nb3n3001

Manufacturer Part Number
nb3n3001
Description
3.3 V 106.25 Mhz/ 212.5 Mhz Pureedge Clock Generator With Lvpecl Differential Output
Manufacturer
ON Semiconductor
Datasheet

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NB3N3001
3.3 V 106.25 MHz/ 212.5 MHz
PureEdge Clock Generator with
LVPECL Differential Output
Description
generator. It accepts a standard 26.5625 MHz fundamental mode AT cut
parallel resonant crystal as the reference source for its integrated crystal
oscillator and low noise phase−locked loop (PLL) and produces user
selectable clock frequencies of either 106.25 MHz or 212.5 MHz.
square−wave through a pair of differential LVPECL clock outputs.
Typical phase jitter at 106.25 MHz is 0.3 ps RMS from 637 kHz to
10 MHz.
the OE pin set LOW. The NB3N3001 operates from a single +3.3 V
supply, and is available in both plastic package and die form. The
operating temperature range is from −40°C to +85°C.
cost, flexibility, and high performance which makes it ideal for
Fibre−Channel applications.
Features
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 1
26.5625 MHz
The NB3N3001 is a low−jitter, dual−rate PLL−synthesized clock
In addition, the PLL circuitry will generate a 50% duty cycle
The LVPECL output drivers can be disabled to high impedance with
The NB3N3001 device provides the optimum combination of low
(637 kHz − 10 MHz): 0.3 ps (Typical)
Phase Noise:
PureEdge Clock Family Provides Accuracy and Precision
Selectable Output Frequency of 106.25 MHz or 212.5 MHz
Crystal Oscillator Interface Designed for a 26.5625 MHz Crystal
Fully Integrated Phase−Lock−Loop with Internal Loop Filter
Differential 3.3 V LVPECL Outputs
Exceeds Bellcore and ITU Jitter Generation Specification
RMS Phase Jitter @ 106.25 MHz, using a 26.5625 MHz Crystal
RMS Phase Noise at 106.25 MHz
Operating Range: V
−40°C to +85°C Ambient Operating Temperature
Small Footprint 8−pin TSSOP Package
This is a Pb−Free Device
Offset
100 Hz −108 dBc/Hz
1 kHz
10 kHz −135 dBc/Hz
100 kHz −135 dBc/Hz
X
Noise Power
−122 dBc/Hz
OUT
X
IN
CC
Oscillator
Crystal
= 3.135 V to 3.465 V
Detector
Phase
Figure 1. Logic Diagram
M = B32
Charge
Pump
1
850 MHz
VCO
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
CASE 948S
DT SUFFIX
TSSOP−8
ORDERING INFORMATION
N =B8
A
Y
WW = Work Week
G
orB4
FSEL
http://onsemi.com
= Assembly Location
= Year
= Pb−Free Package
LVPECL
Output
Publication Order Number:
MARKING
DIAGRAM
Q
Q
YWW
NB3N3001/D
301
AG
106.25 MHz
212.5 MHz
or

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nb3n3001 Summary of contents

Page 1

... Typical phase jitter at 106.25 MHz is 0.3 ps RMS from 637 kHz to 10 MHz. The LVPECL output drivers can be disabled to high impedance with the OE pin set LOW. The NB3N3001 operates from a single +3.3 V supply, and is available in both plastic package and die form. The operating temperature range is from −40°C to +85°C. ...

Page 2

... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NB3N3001 8 VCC Table 1. Output Frequency Select ...

Page 3

... Table 8. PIN CHARACTERISTICS Symbol Parameter C Input Capacitance IN R Input Pull Down Resistor PD Table 9. CRYSTAL CHARACTERISTICS Parameter Frequency Equivalent Series Resistance (ESR) Shunt Capacitance NB3N3001 = 3.3 V ±5 −40°C to 85° Conditions Included 3.3 V ±5 −40°C to 85°C CC ...

Page 4

... Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Please refer to the Phase Noise Plot. 4. Output terminated with − 2.0 V. See Figures 4 and 12. CC NB3N3001 = 3.3 V ±5 −40°C to 85°C (Note 4 Conditions 24 MHz − ...

Page 5

... Figure 4. Output Load AC Test Circuit (Split Power Supply Pulse Width t PERIOD t PW odc + t PERIOD Figure 6. Output Duty Cycle/Pulse Width/Period NB3N3001 Phase Noise Plot SCOPE RMS + Area Under the Masked Phase Noise Plot Figure 5. RMS Phase Jitter Q Clock ...

Page 6

... Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The NB3N3001 also generates sub−nanosecond output edge rates, and therefore, a good power supply bypassing scheme is a must. ...

Page 7

... PCB layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the NB3N3001 outputs imperative that low inductance chip capacitors are used equally important that the board layout not introduce any of the inductance saved by using the leadless capacitors ...

Page 8

... L 6.40 BSC 0.252 BSC −−− 2.20 −−− 0.087 P1 −−− 3.20 −−− 0.126 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB3N3001/D ...

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