adclk954 Analog Devices, Inc., adclk954 Datasheet
adclk954
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adclk954 Summary of contents
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... ATE and high performance instrumentation GENERAL DESCRIPTION GENERAL DESCRIPTION The ADCLK954 is an ultrafast clock fanout buffer fabricated on The ADCLK954 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germa- the Analog Devices, Inc., proprietary XFCB3 silicon germa- nium (SiGe) bipolar process ...
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... ADCLK954 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Electrical Characteristics ............................................................. 3 Absolute Maximum Ratings ............................................................ 5 Determining Junction Temperature .......................................... 5 ESD Caution .................................................................................. 5 REVISION HISTORY 3/09—Revision 0: Initial Version Thermal Performance ...................................................................5 Pin Configuration and Function Descriptions ..............................6 Typical Performance Characteristics ..............................................7 Functional Description .....................................................................9 Clock Inputs ...................................................................................9 Clock Outputs ...
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... Rev Page ADCLK954 Unit Test Conditions/Comments p-p ±1.7 V between input pins pF Ω Ω kΩ Open μ Ω − 2 Ω − 2.0 V) ...
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... ADCLK954 Table 3. Input Select Control Pin Parameter Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance Table 4. Power Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection 1 Output Swing Supply Rejection 2 1 Change in t per change in V ...
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... Description θ JA Per JEDEC JESD51-2 θ Per JEDEC JESD51-6 JMA θ JB Per JEDEC JESD51-8 θ JC Per MIL-STD 883, Method 1012.1 Ψ JT Per JEDEC JESD51-2 Rev Page ADCLK954 + (Ψ × can be used for a first-order approxi- JA θ × Value 46.1 40.3 36 ...
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... Q1, Q1 Differential LVPECL Outputs. 38, 39 Q0, Q0 Differential LVPECL Outputs. (41) EPAD EPAD must be connected to V IN_SEL CLK0 CLK0 REF ADCLK954 TOP VIEW CLK1 (Not to Scale) CLK1 ...
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... Figure 6. LVPECL Output Waveform @ 1000 MHz 214 213 212 211 210 209 208 207 –40 – TEMPERATURE (°C) Figure 7. Propagation Delay vs. Temperature, V 230 220 +85°C 210 +25°C 200 –40°C 190 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 DC COMMON-MODE VOLTAGE (V) Input Slew Rate > 25 V/ns ADCLK954 1.6 V p-p ID 2.7 2.9 3.1 ...
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... ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A –100 WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672), WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D). –110 –120 –130 ADCLK954 –140 –150 –160 CLOCK SOURCE –170 10 100 1k 10k ...
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... See Figure 19 through Figure 22 for various clock input termination schemes. Output jitter performance is degraded by an input slew rate below 4 V/ns, as shown in Figure 12. The ADCLK954 is specifically designed to minimize added random jitter over a wide input slew rate range. Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate ...
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... Input CLK0 . A Logic 1 on the IN_SEL pin selects Input CLK1 and Input CLK1 . PCB LAYOUT CONSIDERATIONS The ADCLK954 buffer is designed for very high speed applica- tions. Consequently, high speed design techniques must be used to achieve the specified performance critically important to use low impedance supply planes for both the negative supply ...
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... Figure 21. AC Coupling Differential Signals Inputs, Such As LVDS V 50Ω CLK CLK CONNECT REF CAPACITOR FROM V ALTERNATIVELY, V CONNECTED, GIVING A CLEANER LAYOUT AND A 180º PHASE SHIFT. Figure 22. Interfacing to AC-Coupled Single-Ended Inputs Rev Page ADCLK954 V REF V T 50Ω 50Ω CLK CLK REF V REF T 50Ω ...
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... PLANE ORDERING GUIDE Model Temperature Range 1 ADCLK954BCPZ −40°C to +85°C 1 ADCLK954BCPZ-REEL7 −40°C to +85°C 1 ADCLK954/PCBZ RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 6.00 BSC SQ 0.60 MAX 0.50 BSC 5.75 BSC SQ 0 ...