adclk950 Analog Devices, Inc., adclk950 Datasheet
adclk950
Available stocks
Related parts for adclk950
adclk950 Summary of contents
Page 1
... V. output swing of 1.6 V. The ADCLK950 is available in a 40-lead LFCSP and specified The ADCLK950 is available in a 40-lead LFCSP and specified for operation over the standard industrial temperature range of for operation over the standard industrial temperature range of −40°C to +85°C. ...
Page 2
... ADCLK950 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Electrical Characteristics ............................................................. 3 Absolute Maximum Ratings ............................................................ 5 Determining Junction Temperature .......................................... 5 ESD Caution .................................................................................. 5 Thermal Performance .................................................................. 5 REVISION HISTORY 7/09—Revision 0: Initial Version Pin Configuration and Function Descriptions ..............................6 Typical Performance Characteristics ..............................................7 ...
Page 3
... Rev Page ADCLK950 Unit Test Conditions/Comments V V p-p ±1.7 V between input pins pF Ω Ω kΩ Open μ Ω − 2 Ω − 2.0 V) ...
Page 4
... ADCLK950 Table 3. Input Select Control Pin Parameter Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance Table 4. Power Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection 1 Output Swing Supply Rejection 2 1 Change in t per change in V ...
Page 5
... Description θ JA Per JEDEC JESD51-2 θ Per JEDEC JESD51-6 JMA θ JB Per JEDEC JESD51-8 θ JC Per MIL-STD 883, Method 1012.1 Ψ JT Per JEDEC JESD51-2 Rev Page ADCLK950 + (Ψ × can be used for a first-order approxi- JA θ × Value 46.1 40.3 36 ...
Page 6
... Differential LVPECL Outputs. 36, 37 Q1, Q1 Differential LVPECL Outputs. 38, 39 Differential LVPECL Outputs. Q0, Q0 (41) EPAD EPAD must be connected to V IN_SEL 1 PIN 1 INDICATOR CLK0 2 CLK0 ADCLK950 REF TOP VIEW CLK1 6 (Not to Scale) CLK1 REF V 10 ...
Page 7
... TEMPERATURE (°C) Figure 7. Propagation Delay vs. Temperature, V 230 220 +85°C 210 +25°C 200 –40°C 190 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 DC COMMON-MODE VOLTAGE (V) Figure 8. Propagation Delay vs. DC Common-Mode Voltage vs. Temperature, Input Slew Rate > 25 V/ns ADCLK950 1.6 V p-p ID 2.7 2.9 3.1 ...
Page 8
... V) CC Rev Page ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672), WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D). ADCLK950 CLOCK SOURCE 10 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) Figure 11 ...
Page 9
... See Figure 19 through Figure 23 for various clock input termination schemes. Output jitter performance is degraded by an input slew rate below 4 V/ns, as shown in Figure 12. The ADCLK950 is specifically designed to minimize added random jitter over a wide input slew rate range. Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate ...
Page 10
... Input CLK0 . A Logic 1 on the IN_SEL pin selects Input CLK1 and Input CLK1 . PCB LAYOUT CONSIDERATIONS The ADCLK950 buffer is designed for very high speed applica- tions. Consequently, high speed design techniques must be used to achieve the specified performance critically important to use low impedance supply planes for both the negative supply ...
Page 11
... CONNECT REF V x REF 50Ω 50Ω CLKx CLKx ADCLK950 CONNECT AND CLKx. PLACE A T REF BYPASS CAPACITOR FROM GROUND. T ALTERNATIVELY AND CLKx CAN BE T REF CONNECTED, GIVING A CLEANER LAYOUT AND A 180 º ...
Page 12
... PLANE ORDERING GUIDE Model Temperature Range 1 ADCLK950BCPZ −40°C to +85°C 1 ADCLK950BCPZ-REEL7 −40°C to +85°C 1 ADCLK950/PCBZ RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 6.00 BSC SQ 0.60 MAX 0.50 BSC 5.75 BSC SQ 0 ...