adclk905 Analog Devices, Inc., adclk905 Datasheet
adclk905
Available stocks
Related parts for adclk905
adclk905 Summary of contents
Page 1
... High speed line receivers Threshold detection Converter clocking GENERAL DESCRIPTION The ADCLK905 (one input, one output), ADCLK907 (dual one input, one output), and ADCLK925 (one input, two outputs) are ultrafast clock/data buffers fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. ...
Page 2
... ADCLK905/ADCLK907/ADCLK925 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuits........................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 REVISION HISTORY 8/07—Revision 0: Initial Version Typical Performance Characteristics ..............................................8 Applications Information .............................................................. 11 Power/Ground Layout and Bypassing..................................... 11 Output Stages ...
Page 3
... R F −138 −144 −152 −159 −161 −161 −135 −145 −153 −160 −161 −161 Rev Page ADCLK905/ADCLK907/ADCLK925 Unit Conditions V CC − 0 p-p −40°C to +85°C (±1.7 V between input pins) V p-p 85°C to 125°C (±1.4 V between input pins) pF Ω Ω ...
Page 4
... ADCLK905/ADCLK907/ADCLK925 Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current ADCLK905 Negative Supply Current Positive Supply Current ADCLK907 Negative Supply Current Positive Supply Current ADCLK925 Negative Supply Current Positive Supply Current 1 Power Supply Rejection 2 Output Swing Supply Rejection 1 Change in T per change in V ...
Page 5
... V Table 3. Thermal Resistance Package Type V − 0 16-lead LFCSP ±40 mA ESD CAUTION ±1 0 ± − −40°C to +125°C 150°C −65°C to +150°C Rev Page ADCLK905/ADCLK907/ADCLK925 θ Unit JA 70 °C/W ...
Page 6
... ADCLK905/ADCLK907/ADCLK925 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions for 1:1 ADCLK905 Buffer Pin No. Mnemonic Description 1 D Noninverting Input Inverting Input Connect. No physical connection to the die Negative Supply Voltage Positive Supply Voltage Inverting Output ...
Page 7
... It can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal at the corners of the package is connected to this back surface. Allow sufficient clearance to vias and other components. ADCLK905/ADCLK907/ADCLK925 PIN ...
Page 8
... ADCLK905/ADCLK907/ADCLK925 TYPICAL PERFORMANCE CHARACTERISTICS 25°C, outputs terminated 50 Ω 2.37V Q Q 1.37V 200ps/DIV Figure 7. Output Waveform, V –90 AGILENT E5500 CARRIER: 122.88MHz NO SPURS –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k 100k f (Hz) Figure 8. Phase Noise at 122.88 MHz – ...
Page 9
... Power Supply Voltage OD 0.07 0.06 +125°C 0.05 +25°C –55°C 0.04 0.03 +125°C 0.02 +25°C –55°C 0.01 0 2.5 3.0 3.5 POWER SUPPLY VOLTAGE (V) Figure 14. Power Supply Current vs. Power Supply Voltage, ADCLK905 110 105 +125°C 100 +25°C 95 –55°C 90 1.6 2.1 2.6 INPUT COMMON MODE (V) Figure 15. Propagation Delay vs Input Swing = 200 mV ICM 0.09 0.08 0.07 0.06 ...
Page 10
... ADCLK905/ADCLK907/ADCLK925 Figure 19. 2.488 Gbps PRBS 2 − 1 with OC-48/STM-16 Mask, Measured p-p Jitter 8.1 ps, Source p-p Jitter 3 Figure 20. 9.95 Gbps PRBS 2 − 1 with OC-193/STM-64 Mask, Measured p-p Jitter 10.5 ps, Source p-p Jitter 6 Figure 21. 4.25 Gbps PRBS 2 − 1 with FC4250 (Optical) Mask, Measured p-p Jitter 8.2 ps, Source p-p Jitter 3.4 ps 58ps/DIV Figure 22 ...
Page 11
... OUTPUT STAGES The specified performance can be achieved only by using proper transmission line terminations. The outputs of the ADCLK905/ ADCLK907/ADCLK925 buffers are designed to directly drive 800 mV into 50 Ω cable or microstrip/stripline transmission lines terminated with 50 Ω referenced to V output stage is shown in Figure 25 ...
Page 12
... ADCLK905/ADCLK907/ADCLK925 TYPICAL APPLICATION CIRCUITS REF CONNECT Figure 26. Interfacing to CML Inputs V REF – CONNECT − 2V Figure 27. Interfacing to PECL CONNECT V T NOTES 1. PLACING A BYPASS CAPACITOR FROM V TO GROUND CAN IMPROVE T THE NOISE PERFORMANCE. ...
Page 13
... REF 6 REF C26 REF 15 V .1UF C15 16 Figure 30. Evaluation Board Schematic Rev Page ADCLK905/ADCLK907/ADCLK925 06318-031 .1UF 1 C35 .1UF C34 .1UF C33 .1UF C32 1 .1UF 1 C8 .1UF C7 .1UF C6 .1UF C5 .1UF C4 .1UF C3 .1UF C2 .1UF C1 2 ...
Page 14
... ADCLK907BCPZ-R7 −40°C to +125°C 1 ADCLK907BCPZ-R2 −40°C to +125°C 1 ADCLK925BCPZ-WP −40°C to +125°C ADCLK925BCPZ-R7 1 −40°C to +125°C 1 ADCLK925BCPZ-R2 −40°C to +125°C ADCLK905/PCBZ 1 1 ADCLK907/PCBZ 1 ADCLK925/PCBZ RoHS Compliant Part. 3.00 0.60 MAX BSC SQ 0. 2.75 TOP ...
Page 15
... NOTES ADCLK905/ADCLK907/ADCLK925 Rev Page ...
Page 16
... ADCLK905/ADCLK907/ADCLK925 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06318-0-8/07(0) Rev Page ...