adclk948 Analog Devices, Inc., adclk948 Datasheet
adclk948
Available stocks
Related parts for adclk948
adclk948 Summary of contents
Page 1
... V. output swing of 1.6 V. The ADCLK948 is available in a 32-lead LFCSP and specified The ADCLK948 is available in a 32-lead LFCSP and specified for operation over the standard industrial temperature range of for operation over the standard industrial temperature range of −40°C to +85°C. ...
Page 2
... ADCLK948 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Electrical Characteristics ............................................................. 3 Absolute Maximum Ratings ............................................................ 5 Determining Junction Temperature .......................................... 5 ESD Caution .................................................................................. 5 Thermal Performance .................................................................. 5 REVISION HISTORY 7/09—Revision 0: Initial Version Pin Configuration and Function Descriptions ..............................6 Typical Performance Characteristics ..............................................7 ...
Page 3
... Rev Page ADCLK948 Unit Test Conditions/Comments V V p-p ±1.7 V between input pins pF Ω Ω kΩ Open μ Ω − 2 Ω − 2.0 V) ...
Page 4
... ADCLK948 Table 3. Input Select Control Pin Parameter Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance Table 4. Power Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection 1 Output Swing Supply Rejection 2 1 Change in t per change in V ...
Page 5
... Description θ JA Per JEDEC JESD51-2 θ Per JEDEC JESD51-6 JMA θ JB Per JEDEC JESD51-8 θ JC Per MIL-STD 883, Method 1012.1 Ψ JT Per JEDEC JESD51-2 Rev Page ADCLK948 + (Ψ × can be used for a first-order approxi- JA θ × Value 49.8 43.5 39 ...
Page 6
... Q3, Q3 23, 24 Q2, Q2 27, 28 Q1, Q1 29 IN_SEL (33) EPAD CLK0 PIN 1 CLK0 INDICATOR REF ADCLK948 CLK1 TOP VIEW (Not to Scale) CLK1 REF NOTES CONNECT. ...
Page 7
... Figure 6. LVPECL Output Waveform @ 1000 MHz 214 213 212 211 210 209 208 207 –40 – TEMPERATURE (°C) Figure 7. Propagation Delay vs. Temperature, V 230 220 +85°C 210 +25°C 200 –40°C 190 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 DC COMMON-MODE VOLTAGE (V) Input Slew Rate > 25 V/ns ADCLK948 1.6 V p-p ID 2.7 2.9 3.1 ...
Page 8
... V). CC Rev Page ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672), WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D). ADCLK948 CLOCK SOURCE 10 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) Figure 11 ...
Page 9
... See Figure 19 through Figure 23 for various clock input termination schemes. Output jitter performance is degraded by an input slew rate below 4 V/ns, as shown in Figure 12. The ADCLK948 is specifically designed to minimize added random jitter over a wide input slew rate range. Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate ...
Page 10
... Input CLK0 . A Logic 1 on the IN_SEL pin selects Input CLK1 and Input CLK1 . PCB LAYOUT CONSIDERATIONS The ADCLK948 buffer is designed for very high speed applica- tions. Consequently, high speed design techniques must be used to achieve the specified performance critically important to use low impedance supply planes for both the negative supply ...
Page 11
... CONNECT REF V x REF 50Ω 50Ω CLKx CLKx ADCLK948 CONNECT AND CLKx. PLACE A T REF BYPASS CAPACITOR FROM GROUND. T ALTERNATIVELY AND CLKx CAN BE T REF CONNECTED, GIVING A CLEANER LAYOUT AND A 180º ...
Page 12
... ORDERING GUIDE Model Temperature Range 1 ADCLK948BCPZ −40°C to +85°C 1 ADCLK948BCPZ-REEL7 −40°C to +85°C 1 ADCLK948/PCBZ RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 5.00 BSC SQ 0.60 MAX 0.50 TOP BSC 4 ...