lmk02002 National Semiconductor Corporation, lmk02002 Datasheet - Page 10

• Manufacturer Part Number: lmk02002
• Description: Precision Clock Conditioner With Integrated Pll
• Manufacturer: National Semiconductor Corporation

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2.3 REGISTER R4 to R7
Registers R4 through R7 control the eight clock outputs. Reg-
ister R4 controls CLKout0, Register R5 controls CLKout1, and
so on. There is one additional bit in register R0 called RESET.
Aside from this, the functions of these bits are identical. The
X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and
CLKoutX_EN denote the actual clock output which may be
from 0 to 3.
2.3.1 RESET bit -- R0 only
This bit is only in register R0. The use of this bit is optional
and it should be set to '0' if not used. Setting this bit to a '1'
forces all registers to their power on reset condition and there-
fore automatically clears this bit. If this bit is set, all other R0
bits are ignored and R0 needs to be programmed again if
used with its proper values and RESET = 0.
2.3.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers
These bits control the Clock Output Multiplexer for each clock
output. Changing between the different modes changes the
RESET
CLKoutX_
MUX
CLKoutX_E
N
CLKoutX_
DIV
CLKoutX_
DLY
DIV4
EN_CLKou
t_Global
POWERD
OWN
PLL_CP_T
RI
PLL_CP_P
OL
PLL_MUX
PLL_R
PLL_CP_G
AIN
PLL_N
Bit Name
Def
760 N divider =
aul
Val
Bit
ue
10 R divider = 10 PLL R divide
0
0
0
1
0
0
1
0
0
0
0
0
t
No reset,
normal
operation
Bypassed
Disabled
Divide by 2
0 ps
PDF
MHz
Normal -
CLKouts
normal
Normal -
Device active
Normal - PLL
active
Negative
Polarity CP
Disabled
100 uA
760
Bit State
≤
20
Reset to
power on
defaults
CLKoutX mux
mode
CLKoutX
enable
CLKoutX
clock divide
CLKoutX
clock delay
Phase
Detector
Frequency
Global clock
output enable
Device power
down
TRI-STATE
PLL charge
pump
Polarity of
charge pump
Multiplexer
control for LD
pin
value
Charge pump
current
PLL N divide
value
Description
Bit
gis
Re
ter
R0
R4
R7
R1
R1
R1
to
1
4
5
cati
18:
15:
7:4
23:
19:
31:
25:
Bit
Lo
on
31
17
16
15
27
26
25
24
20
30
8
8
8
10
blocks in the signal path and therefore incurs a delay relative
to the bypass mode. The different MUX modes and associ-
ated delays are listed below.
2.3.3 CLKoutX_DIV[7:0] -- Clock Output Dividers
These bits control the clock output divider value. In order for
these dividers to be active, the respective CLKoutX_MUX
(See 2.3.2) bit must be set to either "Divided" or "Divided and
Delayed" mode. After all the dividers are programed, the
SYNC* pin must be used to ensure that all edges of the clock
outputs are aligned (See 1.7). The Clock Output Dividers fol-
low the VCO Divider so the final clock divide for an output is
VCO Divider × Clock Output Divider. By adding the divider
block to the output path a fixed delay of approximately 100 ps
is incurred.
The actual Clock Output Divide value is twice the binary value
programmed as listed in the table below.
2.3.4 CLKoutX_DLY[3:0] -- Clock Output Delays
These bits control the delay stages for each clock output. In
order for these delays to be active, the respective
CLKoutX_MUX (See 2.3.2) bit must be set to either "Delayed"
or "Divided and Delayed" mode. By adding the delay block to
the output path a fixed delay of approximately 400 ps is in-
curred in addition to the delay shown in the table below.
CLKoutX_MUX
0
0
0
0
0
0
1
.
CLKoutX_DLY[3:0]
0
0
0
0
0
0
1
[1:0]
.
0
1
2
3
CLKoutX_DIV[7:0]
0
0
0
0
0
0
1
.
0
1
2
3
4
5
6
7
8
0
0
0
0
0
0
1
.
Bypassed (default)
0
0
0
0
0
0
1
Divided and
.
Delayed
Delayed
Divided
Mode
0
0
0
0
1
1
1
.
0
0
1
1
0
0
1
.
Delay (ps)
0 (default)
0
1
0
1
0
1
1
.
(In addition to the
(In addition to the
1050
1200
Bypass Mode
150
300
450
600
750
900
Added Delay
programmed
programmed
Relative to
Clock Output
Divider value
100 ps
400 ps
500 ps
2 (default)
delay)
delay)
0 ps
Invalid
510
10
...
4
6
8