lmk03000c National Semiconductor Corporation, lmk03000c Datasheet - Page 10
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lmk03000c
Manufacturer Part Number
lmk03000c
Description
Precision Clock Conditioner With Integrated Vco
Manufacturer
National Semiconductor Corporation
Datasheet
1.LMK03000C.pdf
(26 pages)
www.national.com
1.8 CLKout OUTPUT STATES
Each clock output may be individually enabled with the
CLKoutX_EN bits. Each individual output enable control bit is
gated with the Global Output Enable input pin (GOE) and the
Global Output Enable bit (EN_CLKout_Global).
All clock outputs can be disabled simultaneously if the GOE
pin is pulled low by an external signal or EN_CLKout_Global
is set to 0.
When an LVDS output is in the Off state, the outputs are at a
voltage of approximately 1.5 volts. When an LVPECL output
Don't care
CLKoutX
_EN bit
1
0
1
EN_CLKout
_Global bit
Don't care
1
0
1
Don't care
Don't care
High / No
GOE pin
Connect
0
Output State
Clock X
Enabled
Low
Off
Off
10
is in the Off state, the outputs are at a voltage of approximately
1 volt.
1.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT
The GOE pin provides an internal pull-up resistor as shown
on the functional block diagram. If it is not terminated exter-
nally, the clock output states are determined by the Clock
Output
EN_CLKout_Global bit.
By programming the PLL_MUX register to Digital Lock Detect
Active High (See 2.6.2), the Lock Detect (LD) pin can be con-
nected to the GOE pin in which case all outputs are set low
automatically if the synthesizer is not locked.
1.10 POWER ON RESET
When supply voltage to the device increases monotonically
from ground to Vcc, the power on reset circuit sets all registers
to their default values, see 2.3.1 for more information on de-
fault register values. Voltage should be applied to all Vcc pins
simultaneously.
Enable
bits
(CLKoutX_EN)
and
the