APP530 Agere Systems, APP530 Datasheet - Page 2

• Manufacturer Part Number: APP530
• Description: Edge/access And Multiservice Network Processors: APP550 And APP530
• Manufacturer: Agere Systems

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Product Brief
May 2003
Features and Benefits
Agere Systems’ devices provide significant features and
benefits as you build multiservice applications. These include:
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Flexible Multiprotocol Support at Up to Full-Duplex Line
Rates
Agere Systems patented programmable hardware engine,
the Pattern Processing Engine (PPE), enables you to
support multiple protocols.
Protocols include:
—IP/ATM
—Frame Relay/ATM
—MPLS/ATM
—EFT Martini Draft “Transport of Layer 2 Frames Over
—FRF8.1 Service Interworking Between ATM and FR
Wire-Rate Bidirectional AAL5 SAR
AAL5 SAR capabilities are embedded in the APP550 and
APP530. This enables the flexible hardware engines to
achieve bidirectional line rates without sacrificing protocol
interworking flexibility.
Per-Connection Policing and Statistics
The APP550 and APP530 support packet- or cell-based
policing algorithms. Policing and statistics can be managed
on up to 128k VCs or packet flows.
Configurable Class Buffer Management Across 256K
Queues
Programmable classes and thresholds allow you to use any
standard or proprietary buffer management algorithms.
Operations, Administration, and Maintenance (OAM)
The APP550 and APP530 provide complete OAM support in
compliance with I.610 for ATM. In addition, the flexible and
programmable OAM mechanisms in both devices can be
used to support evolving OAM standards for Multiprotocol
Label Switching (MPLS).
Hierarchical Scheduling for ATM Cells and Packets
The extensive scheduling capabilities of the APP550 and the
APP530 enable you to meet the strict scheduling
requirements for ATM and packet applications. The five level
hierarchical scheduling system enables traffic management
at multiple levels, and ensures that both cell and packet
requirements are met.
—Quality of Service (QoS) can be attained for constant bit
MPLS” (www.ietf.org)
PVCs (www.ietf.org)
rate (CBR), real-time variable bit rate (VBR-rt), nonreal-
time variable bit rate, (VBR-nrt), and unspecified bit rate
(UBR, UBR+) traffic shaping.
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Interfaces
Both chips support these standards through a 32-bit interface:
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A second SPI-3 interface can be directed to a switch fabric or
coprocessor to support additional functions. See the figure
below.
POS-PHY to optional
POS-PHY to optional
co-processor
co-processor
—Class-based scheduling, such as that used by strict
Configurable Payload Segmentation
The flexibility of these chips allows you to support different
fabric and network payload cell sizes, from 40 to 64 bytes.
Integrated Ethernet MACs
Both chips include 4x1000 and 16x10/100 integrated
Ethernet MACs to accommodate applications where ATM
must be terminated to an Ethernet link. These MACs can
also be used to develop high port density, space-efficient
Ethernet applications that support technologies such as
Virtual LANS (VLANS) and bridging.
Coprocessor Support
Support for AAL2 SAR or a security processor is enabled
through the standard SPI-3 coprocessor port. With this port,
you can customize the APP550 and APP530 using either off-
the-shelf logic or your own specific logic. Agere Systems also
offers a compatible AAL2 SAR coprocessor.
SPI-3
UTOPIA Level 2
UTOPIA Level 3
GMII (4 integrated GbE MACs)
SMII (16 integrated 10/100 MACs)
GMII/SMII or
GMII/SMII or
POS-PHY/Utopia
POS-PHY/Utopia
PHY
PHY
priority, weighted round robin (WRR), and deficit-
weighted round robin (DWRR), can be performed as a
standalone scheme or in conjunction with the rate
shapers.
APP550
APP550
APP530
APP530
APP550 and APP530
PCI to Host CPU
PCI to Host CPU
Fabric
Fabric