sy58040u Micrel Semiconductor, sy58040u Datasheet - Page 3

• Manufacturer Part Number: sy58040u
• Description: Sy58040u Ultra Precision 4x4 Cml Switch With Internal I/o Termination
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
M9999-112707
[e-mail] or [phone]
12, 13, 20, 21,
35, 36, 43, 44 Exposed pad
Pin Number
PACKAGE/ORDERING INFORMATION
VREF-AC1
VREF-AC2
28, 31, 34
PIN DESCRIPTION
6, 22, 25,
CONFIG
17, 15,
23, 24,
26, 27,
41, 39
29, 30
32, 33
10, 8,
16, 9,
3, 40
4, 2,
LOAD
14,
11,
42
18
19
38
37
1,
VCC
5
7
VT1
/IN2
VT2
/IN1
IN1
IN2
44-Pin MLF
10
11
1
2
3
4
5
6
7
8
9
44 43 42 41 40 39 38 37
12 13 14 15 16 17 18 19
VRef_AC0
VRef_AC1
VRef_AC2
VRef_AC3
Pin Name
VT0, VT1
VT2, VT3
IN0, /IN0
IN1, /IN1
IN2, /IN2
IN3, /IN3
Q0, /Q0,
Q1, /Q1,
Q2, /Q2,
Q3, /Q3,
SOUT0
SOUT1
CONF,
LOAD
GND,
SIN0
SIN1
VCC
®
(MLF-44)
36
20 21 22
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept
AC or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin
through 50Ω. Note that these inputs will default to an indeterminate state if left open. Please refer to
the “Input Interface Applications” section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT
pins provide a center-tap to a termination network for maximum interface flexibility. See “Input
Interface Applications” section for more details.
Reference Voltage: This output biases to V
Connect VRef-AC output pin to the VT input pin. Bypass each VRef-AC pin with a 0.01µF low ESR
capacitor to V
These single-ended TTL/CMOS-compatible inputs address the data inputs. Note that these inputs
are internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open.
These single-ended TTL/CMOS-compatible inputs address the data outputs. Note that these inputs
are internally connected to a 25kΩ pullup resistor and will default to a logic HIGH state if left open.
These single-ended TTL/CMOS compatible inputs control the transfer of the addresses to the
internal multiplexers. See “Address Tables” and “Timing Diagram” sections for more details. Note
that these inputs are internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH
state if left open.
Configuration Sequence
1. Load: Loads configuration into buffer, while Configuration Buffer holds existing switch configuration.
2. Configuration: Loads new configuration into the Configuration Buffer and updates switch configuration.
Buffer Mode
The SY58040U defaults to buffer mode (IN-to-Q) if the load and configuration control signals are
floating.
Differential Outputs: These CML output pairs are the outputs of the device. Please refer to the truth
table below for details. Unused output pairs may be left open. Each output is designed to drive
400mV into 100Ω across the pair, or 50Ω to V
Positive power supply. Bypass with 0.1µF//0.01µF low ESR capacitors and place as close to each
V
Ground. GND and EPad must both be connected to most negative potential of chip ground.
35
CC
34
pin.
24
23
33
32
31
30
29
28
27
26
25
/Q3
Q3
VCC
/Q2
Q2
VCC
/Q1
Q1
VCC
/Q0
Q0
CC
. See “Input Interface Applications” section for more details.
Ordering Information
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
Part Number
SY58040UMI
SY58040UMITR
SY58040UMY
SY58040UMYTR
(3)
3
(2)
(2, 3)
Package Operating
CC
MLF-44
MLF-44
MLF-44
MLF-44
Type
CC
–1.2V. It is used when AC coupling the inputs.
.
(1)
Industrial
Industrial
Industrial
Industrial
Range
SY58040U Pb-Free
SY58040U Pb-Free
bar-line indicator
bar-line indicator
SY58040U
SY58040U
Package
Marking
A
= 25°C, DC electricals only.
Matte-Sn
Matte-Sn
Pb-Free
Pb-Free
SY58040U
Finish
Sn-Pb
Sn-Pb
Lead