w83194br-sd Winbond Electronics Corp America, w83194br-sd Datasheet - Page 13

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w83194br-sd

Manufacturer Part Number
w83194br-sd
Description
Winbond Clock Generator For Intel P4 Springdale Series Chipset
Manufacturer
Winbond Electronics Corp America
Datasheet
Table-1: Clock output mode selection
7.6
AGP/PCI over clock
BIT
7
6
5
4
3
2
1
0
CPU over clock
SRC over clock
Spreading
Register 5: Watchdog Control (Default = 00H)
MODE1/0
MODE
WD_TIMEOUT
SAF_FREQ [4]
SAF_FREQ [3]
SAF_FREQ [2]
SAF_FREQ [1]
SAF_FREQ [0]
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
EN_WD
SEL24
NAME
PWD
NORMAL MODE
X
0
0
0
0
0
0
0
All clocks are
Byte 8 & 9
Byte 8 & 9
Byte 8 & 9
Effective
Program this bit =>
Pin 21 24 / 48 MHz output selection
1: 24 MHz, 0: 48 MHz. (Default)
Default value follow hardware trapping data on SEL24_48# pin.
1: Enable Watchdog Timer feature.
0: Disable Watchdog Timer feature.
Read-back this bit =>
During timer count down the bit read back to 1.
If count to zero, this bit read back to 0
Read Back only. Timeout Flag.
1: Watchdog has ever started and counts to zero.
0: Watchdog is restarted and counting.
These bits will be reloaded in Reg-0 to select frequency table. As the
watchdog is timeout and EN_SAFE_FREQ = 1.
00
CPU is effective Only.
W83194BR-SD/W83194BG-SD
CPU OVER CLOCK
- 9 -
(asynchronous)
(asynchronous)
Byte 4 & 10
Byte 4 & 10
Byte 8 & 9
MODE
01
DESCRIPTION
Publication Release Date: March, 22, 2006
CPU and SRC are Effective.
OVER CLOCK MODE
(asynchronous)
Byte 4 & 10
Byte 8 & 9
Byte 8 & 9
CPU/SRC
10
Revision 1.2

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