nb6lq572 ON Semiconductor, nb6lq572 Datasheet - Page 3

• Manufacturer Part Number: nb6lq572
• Description: 2.5v / 3.3v Differential 4 1 Mux W/input Equalizer To 1 2 Lvpecl Clock/data Fanout / Translator
• Manufacturer: ON Semiconductor

1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or
2. All V
Table 2. PIN DESCRIPTION
Pin Num-
10, 13, 16
17, 20, 23
25, 28
29, 32
26, 30
14, 19
21, 22
left open, and if no signal is applied on INx/INx input, then the device will be susceptible to self−oscillation.
11, 12
9, 24
ber
1, 4
5, 8
2, 6
15
18
27
31
3
7
−
CC
and GND pins must be externally connected to a power supply for proper operation.
Pin Name
VREFAC0
VREFAC1
VREFAC2
VREFAC3
VT0, VT1
VT2, VT3
IN0, IN0
IN1, IN1
IN2, IN2
IN3, IN3
Q0, Q0
Q1, Q1
SEL0
SEL1
GND
V
NC
EP
CC
LVTTL/LVCMOS
LVPECL Output
LVPECL, CML,
LVDS Input
Input
I/O
−
−
−
−
Noninverted, Inverted, Differential Clock or Data Inputs
Internal 100 W Center−tapped Termination Pin for INx / INx
Input Select pins, default HIGH when left open through a 94 kW pullup resistor.
Input logic threshold is V
No Connect
Positive Supply Voltage.
Non−inverted, Inverted Differential Outputs.
Negative Supply Voltage
Output Voltage Reference for Capacitor−Coupled Inputs
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is electrically connected to the die, and
must be electrically connected to GND.
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3
CC
/ 2. See Select Function, Table 1.
Pin Description