nb6l11m ON Semiconductor, nb6l11m Datasheet

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nb6l11m

Manufacturer Part Number
nb6l11m
Description
2.5v / 3.3v 1 2 Differential Cml Fanout Buffer
Manufacturer
ON Semiconductor
Datasheet

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nb6l11mMNG
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NB6L11M
2.5V / 3.3V 1:2 Differential
CML Fanout Buffer
Multi-Level Inputs w/ Internal Termination
Description
differential inputs incorporate internal 50 W termination resistors that
are accessed through the V
LVTTL, CML, or LVDS logic levels.
to this device only. V
single-ended PECL or NECL inputs. For all single-ended input
conditions, the unused complementary differential input is connected
to V
capacitor-coupled inputs. When used, decouple V
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
high performance clock products.
Features
© Semiconductor Components Industries, LLC, 2007
September, 2007 - Rev. 2
The NB6L11M is a differential 1:2 CML fanout buffer. The
The V
The device is housed in a small 3x3 mm 16 pin QFN package.
The NB6L11M is a member of the ECLinPS MAXt family of
EP, and SG Devices
Maximum Input Clock Frequency > 4 GHz, Typical
225 ps Typical Propagation Delay
70 ps Typical Rise and Fall Times
0.5 ps maximum RMS Clock Jitter
Differential CML Outputs, 380 mV peak-to-peak, typical
LVPECL Operating Range: V
NECL Operating Range: V
Internal Input Termination Resistors, 50 W
VREFAC Reference Output
Functionally Compatible with Existing 2.5 V / 3.3V LVEL, LVEP,
-40°C to +85°C Ambient Operating Temperature
These are Pb-Free Devices
REFAC
REFAC
as a switching reference voltage. V
pin is an internally generated voltage supply available
REFAC
REFAC
output should be left open.
T
pins and will accept LVPECL, LVCMOS,
CC
is used as a reference voltage for
CC
= 0 V with V
= 2.375 V to 3.63 V with V
REFAC
EE
= -2.375 V to -3.63 V
may also rebias
REFAC
1
with a
EE
= 0 V
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional marking information, refer to
VTD
VTD
Application Note AND8002/D.
Figure 1. Simplified Logic Diagram
A
L
Y
W
G
(Note: Microdot may be in either location)
D
D
ORDERING INFORMATION
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
http://onsemi.com
V
MN SUFFIX
CASE 485G
REFAC
QFN-16
Publication Order Number:
1
DIAGRAM*
16
MARKING
ALYWG
NB6L11M/D
NB6L
11M
G
Q0
Q0
Q1
Q1

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nb6l11m Summary of contents

Page 1

... When not used, V output should be left open. REFAC The device is housed in a small 3x3 mm 16 pin QFN package. The NB6L11M is a member of the ECLinPS MAXt family of high performance clock products. Features • Maximum Input Clock Frequency > 4 GHz, Typical • ...

Page 2

... CC EE NB6L11M Exposed Pad (EP VTD NB6L11M D 3 VTD REFAC EE CC Figure 2. Pin Configuration (Top View) Description Internal 50 W Termination Pin for D input. Noninverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD. ...

Page 3

... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. NB6L11M Characteristics Human Body Model Machine Model ...

Page 4

... and V parameters must be complied with simultaneously. IHD ILD, ID CMR 9. V min varies 1:1 with maximum varies 1:1 with V CMR EE CMR input signal. NB6L11M V = 2.375 ...

Page 5

... Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive peak-to-peak data dependent jitter with input NRZ data at PRBS23. 15. Input and output voltage swing is a single-ended measurement operating in differential mode. NB6L11M = 2.375 ...

Page 6

... D D Figure 6. Differential Inputs Driven Differentially IHD(MAX) V ILD(MAX) V IHD CMR ID V ILD V IHD(MIN) V IL(MIN) GND Figure 8. V Diagram CMR NB6L11M VTD VTD Figure 3. Input Structure thmax thmin Figure 7. Differential Inputs Driven Differentially ...

Page 7

... NB6L11M 50 W* Single-Ended Driver 50 W* GND GND Figure 14. Capacitor-Coupled Single-Ended Interface Bypassed Connected Ground with 0.1 mF Capacitor) http://onsemi.com NB6L11M GND Figure 11. LVDS Interface V CC GND V CC ...

Page 8

... Figure 17. Typical CML Termination for Output Driver and Device Evaluation ORDERING INFORMATION Device NB6L11MMNG NB6L11MMNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NB6L11M versus Output OUTPP ...

Page 9

... MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.18 0.30 D 3.00 BSC D2 1.65 1.85 E 3.00 BSC E2 1.65 1.85 e 0.50 BSC K 0.18 TYP L 0.30 0.50 SOLDERING FOOTPRINT* 3.25 0.128 0.30 EXPOSED PAD 0.012 1.50 0.059 0.30 0.012 0.50 0.02 SCALE 10:1 inches ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NB6L11M/D mm ...

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