sy100ep196v Micrel Semiconductor, sy100ep196v Datasheet
sy100ep196v
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sy100ep196v Summary of contents
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... PECL, LVPECL, NECL, or LVNECL The delay varies in discrete steps based on a control CC word presented to SY100EP196V. The 10-bit width of this latched control register allows for delay increments of approximately 10ps. In addition, delay may be varied continuously in about a 30ps range by setting the voltage at the FTUNE pin. ...
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... 10-bit Latch SY100EP196V Operating Package Range Marking Industrial SY100EP196V Industrial SY100EP196V Industrial SY100EP196V with Pb-Free bar-line indicator Industrial SY100EP196V with Pb-Free bar-line indicator = 25°C, DC Electricals only ...
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... Most Positive Supply: Supply ground for NECL systems. Bypass to V 0.01µF low ESR capacitors. 100k ECL Outputs: These outputs are used when cascading two or more SY100EP196V to /CASCADE extend the delay range required. Refer to Table 7 (page 17) for delay values. ...
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... Supply Voltage (V PECL Mode (V Supply Voltage (V NECL Mode (V Ambient Temperature (T +0.5V Package Thermal Resistance CC –0.5V TQFP-32 (θ EE Still-air ............................................................. 50°C/W 500lfpm ............................................................ 42°C/W TQFP-32 (θ Condition No Load, Over Supply Voltage 4 SY100EP196V ( =0V) ............................. +3.0V to +5. =0V) ............................ –3.0V to –5. ......................... –40°C to +85° ..................................................... 20°C/W JC Min Typ Max 3 ...
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... Condition Figures Figures Figures 1, 4 Figures 1, 4 Figure can vary +0.3V to –2.2V range is referenced to the most positive side of the differential input signal. IHCMR 5 ECL Pro® SY100EP196V Min Typ Max Units 2155 2280 2405 mV 1355 1480 1605 mV 2075 ...
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... Figure can vary +2.0V to –0.5V range is referenced to the most positive side of the differential input signal. IHCMR range is referenced to the most positive side of the differential input signal. IHCMR 6 ECL Pro® SY100EP196V Min Typ Max Units 3855 3980 4105 mV 3055 3180 ...
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... SY100EP196V (12, 13) ° ° + + Typ Max Min Typ 2.5 2.5 2050 2600 1950 2250 12200 14000 10600 13300 ...
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... Supply Current vs. Temperature 180 160 140 120 100 -40 - 100 TEMPERATURE (°C) 8 ECL Pro® SY100EP196V Propagation Delay vs. FTUNE Voltage -10 –40 -15 25 -20 85 -25 0 0.5 1 1.5 2 2.5 3 3.5 FTUNE VOLTAGE (V) ...
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... SY100EP196V /EN LEN SETMIN SETMAX D[0:10] 75k Figure 1b. Single-Ended Input Structure M9999-072706 hbwhelp@micrel.com or (408) 955-1690 Figure 3a. Output Levels, PECL, LVPECL 9 SY100EP196V CASCADE /Q, /CASCADE SY100EP196V Figure 2. Emitter Output Structure CASCADE OH /CASCADE CASCADE OL /CASCADE Figure 3b. Output Levels, NECL ...
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... M9999-072706 hbwhelp@micrel.com or (408) 955-1690 0V Invalid V IH(MAX) Logic High V IH(MIN) Invalid V IL(MAX) Logic Low V IL(MIN Invalid Figure 4c. Input Levels, NECL IN /IN Figure 5a. Input Common Mode, PECL, LVPECL IN /IN Figure 5b. Input Common Mode, NECL 10 ECL Pro® SY100EP196V V IHCMR IHCMR V IHCMR ...
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... – +3.3V 82Ω 82Ω Figure 6c. Terminating Unused I/O reference pin . BB . Bypass with a 0.01µF capacitor not GND, as PECL is referenced SY100EP196V +3. – +3.3V “Destination” C1 (optional) 0.01µF = 110Ω. b +3.3V 50Ω 0.01µ ECL Pro® ...
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... SY100EP196V Figure 9c. Connecting CMOS Signals to the D Inputs Note: V and V are not connected +3.3V CC TTL D[0:10] Inputs 1.5k SY100EP196V Figure 9d. Connecting TTL Signals to the D Inputs with +5.0V CC TTL D[0:10] Inputs 500 SY100EP196V Figure 9e. Connecting TTL Signals to the D Inputs with ...
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... PECL, CMOS, or TTL interface standards. Since multiplexers must appear in the delay path, SY100EP196V has a minimum delay of about 2.2ns. Delays below this value are not possible. In addition, when cascading multiple SY100EP196V to extend the delay range, the minimum delay is about 2.2ns times the number of SY100EP196V in cascade ...
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... DAC whose purpose is to provide extremely fine delay EE + 1.5V. Refer to under digital control +4.5V to +5.5V 0V +3.0V to +3. –3.0 to –5.5V Table 6. Signal Path Logic Standard 14 ECL Pro® SY100EP196V CC Delay Control Input Choices PECL, CMOS, TTL LVPECL, CMOS, TTL NECL ...
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... PECL or LVPECL. Figures 9 show how to connect V V for all possible cases. EF Cascading Two or more SY100EP196V may be cascaded, in order to extend the range of delays permitted. Each additional SY100EP196V adds about 2200ps to the minimum delay, and adds another 10240ps to the delay range. is used Internal cascade circuitry has been included in the BB SY100EP196V ...
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... Precision CML Delay Line M9999-072706 hbwhelp@micrel.com or (408) 955-1690 Control Word (12bits) SY100EP196V SY100EP196V C[11] D[10] FTUNE /IN /Q /IN SETMIN SETMIN /CASCADE SETMAX SETMAX CASCADE Figure 10c. Cascading Four SY100EP196V Data Sheet Link http://www.micrel.com/product-info/products/sy100ep195v.shtml http://www.micrel.com/product-info/products/sy55856u.shtml 16 SY100EP196V DAC SY100EP196V C[10] D[10] FTUNE C[9:0] D[9: /IN /Q /CASCADE CASCADE ...
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... Table 7. List of Nominal Delay Values for Cascaded SY100EP196V M9999-072706 hbwhelp@micrel.com or (408) 955-1690 Nominal Delay (ps) One Chip Two Chips Three Chips 2,200 4,400 2,210 4,410 2,220 4,420 2,240 4,440 2,280 4,480 ...
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... Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify M9999-072706 hbwhelp@micrel.com or (408) 955-1690 + 1 (408) 474-1000 FAX WEB Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. 18 SY100EP196V Rev. 01 http://www.micrel.com ECL Pro® ...