ad80164absvz Analog Devices, Inc., ad80164absvz Datasheet - Page 2

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ad80164absvz

Manufacturer Part Number
ad80164absvz
Description
Dual, 12-/14-/16-bit,1 Gsps Digital-to-analog Converters
Manufacturer
Analog Devices, Inc.
Datasheet
AD9776A/AD9778A/AD9779A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 23
Theory of Operation ...................................................................... 24
SPI Register Map............................................................................. 27
Interpolation Filter Architecture .................................................. 31
REVISION HISTORY
8/07—Revision 0: Initial Version
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 5
Digital Input Data Timing Specifications ................................. 6
AC Specifications.......................................................................... 6
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Differences Between AD9776/AD9778/AD9779 and
AD9776A/AD9778A/AD9779A............................................... 24
Serial Peripheral Interface ......................................................... 25
MSB/LSB Transfers..................................................................... 26
Interpolation Filter Minimum and Maximum Bandwidth
Specifications .............................................................................. 35
Driving the REFCLK Input ....................................................... 36
Internal PLL Clock Multiplier/Clock Distribution................ 36
Rev. 0 | Page 2 of 68
Evaluation Board Operation ......................................................... 49
Outline Dimensions ....................................................................... 66
PLL Loop Filter Bandwidth ...................................................... 38
AD9776A/AD9778A/AD9779A PLL Autosearch Feature ... 38
Full-Scale Current Generation ................................................. 38
Using the AD9776A/AD9778A/AD9779A to Correct for
Nonideal Performance of Quadrature Modulators on the IF
to RF Conversion........................................................................ 40
I/Q Channel Gain Matching ..................................................... 40
LO Feedthrough Compensation .............................................. 40
Results of Gain and Offset Correction .................................... 40
Power Dissipation....................................................................... 41
Power-Down and Sleep Modes................................................. 43
Interleaved Data Mode .............................................................. 43
Timing Information ................................................................... 43
Timing Validation of Digital Input Data Bus ............................ 45
Synchronization of Input Data to REFCLK Input (Pin 5 and
Pin 6) with PLL Enabled or Disabled ...................................... 45
Valid Timing Window, SYNC_I to REFCLK and to Internal
DACCLK ..................................................................................... 46
Data Delay Line, Error Correction, Manual Mode................ 47
Data Delay Line, Error Correction Auto Mode ..................... 48
Multiple DAC Synchronization................................................ 48
Modifying the AD9776A/AD9778A/AD9779A Evaluation
Board to Use the ADL5372 On-Board Quadrature
Modulator.................................................................................... 51
Evaluation Board Schematics ................................................... 52
Ordering Guide .......................................................................... 66

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