mc10ep196 ON Semiconductor, mc10ep196 Datasheet

mc10ep196

Manufacturer Part Number

mc10ep196

Description

3.3v/5vecl Programmable Delay Chip With Ftune

Manufacturer

ON Semiconductor

Datasheet

1.MC10EP196.pdf (16 pages)

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primarily for clock deskewing and timing adjustment. It provides variable

delay of a differential NECL/PECL input transition. It is identical to the

EP195 with the exception of the added feature of further tuneability in

delay using the FTUNE pin. The FTUNE input takes an analog voltage

from V

multiplexers as shown in the logic diagram, Figure 2. The delay increment

of the EP196 has a digitally selectable resolution of about 10 ps and a

range of up to 10.2 ns. The required delay is selected by 10 data select

inputs D[0:9] which are latched on chip by a high signal on the latch

enable (LEN) control. The approximate delay values for varying tap

numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 1,

Table 2, and Figure 3.

fixed minimum delay of 2.2 ns. An additional pin, D10, is provided for

cascading multiple PDCs for increased programmable range. The

cascade logic allows full control of multiple PDCs.

combinations of interconnects between V

CMOS, ECL, or TTL level signals. For CMOS input levels, leave V

and V

TTL level operation, connect a 1.5 V supply reference to V

open V

accomplished by placing a 1.5 kW or 500 W resistor between V

this device only. For single–ended input conditions, the unused

differential input is connected to V

and V

to 0.5 mA. When not used, V

This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.

May, 2002 – Rev. 4

The MC10/100EP196 is a programmable delay chip (PDC) designed

The delay section consists of a programmable matrix of gates and

Because the EP196 is designed using a chain of multiplexers, it has a

Select input pins, D0–D10, may be threshold controlled by

The V

The 100 Series contains temperature compensation.

with V

NECL Mode Operating Range: V

with V

Maximum Frequency

PECL Mode Operating Range: V

Open Input Default State

Safety Clamp on Inputs

A Logic High on the EN Pin Will Force Q to Logic Low

D[0:10] Can Accept Either ECL, CMOS, or TTL Inputs

Semiconductor Components Industries, LLC, 2002

for 3.3 V or 5.0 V power supplies, respectively.

may also rebias AC coupled inputs. When used, decouple V

Output Reference Voltage

open. For ECL operation, short V

via a 0.01 mF capacitor and limit current sourcing or sinking

to V

pin. The 1.5 V reference voltage to V

pin, an internally generated voltage supply, is available to

= –3.0 V to –5.5 V

= 0 V

to fine tune the output delay from 0 to 60 ps.

1.8 GHz Typical

should be left open.

as a switching reference voltage.

= 0 V

= 3.0 V to 5.5 V

(pin 7) and V

and V

(pins 7 and 8). For

pin can be

(pin 8) for

and leave

and

MC10EP196FA

MC10EP196FAR2

MC100EP196FA

MC100EP196FAR2

*For additional information, refer to Application Note

AND8002/D

CASE 873A

Device

FA SUFFIX

LQFP–32

ORDERING INFORMATION

XXX = 10 OR 100

WL = Wafer Lot

WW = Work Week

http://onsemi.com

= Assembly Location

= Year

LQFP–32

Package

Publication Order Number:

DIAGRAM*

MARKING

2000 Tape & Reel

AWLYYWW

250 Units/Tray

MCXXX

EP196

MC10EP196/D

Shipping

Related parts for mc10ep196

mc10ep196 Summary of contents

Page 1

... WW = Work Week *For additional information, refer to Application Note AND8002/D ORDERING INFORMATION Device Package Shipping MC10EP196FA LQFP–32 250 Units/Tray MC10EP196FAR2 LQFP–32 2000 Tape & Reel MC100EP196FA LQFP–32 250 Units/Tray MC100EP196FAR2 LQFP–32 2000 Tape & Reel Publication Order Number: MC10EP196/D ...

Page 2

... Internal pulldown will provide logic low if pin left unconnected. ** For TTL Mode, connect appropriate resistor between V *** Short V POWER SUPPLY SUPPLY ( PECL NECL MC10EP196, MC100EP196 V FTUNE CC CC PIN IN*, IN* EN EN* D[0:10]* CASCADE Q, Q CASCADE LEN SETMIN*† SETMAX SETMAX* ...

Page 3

... MC10EP196, MC100EP196 Figure 2. Logic Diagram http://onsemi.com TABLE 1. THEORETICAL DELAY VALUES D10 D(9:0) Value 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 1 XXXXXXXXXX TABLE 2. FTUNE DELAY PIN Input Range V –V ( Delay Value ...

Page 4

... Internal Input Pullup Resistor ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. MC10EP196, MC100EP196 336 420 504 588 TAP Figure 3. Estimated Delay versus Tap Characteristics ...

Page 5

... Input and output parameters vary 1:1 with V 4. All loading with –2.0 volts min varies 1:1 with IHCMR EE IHCMR input signal. MC10EP196, MC100EP196 Condition ...

Page 6

... Required 500 lfpm air flow when using +5 V power supply. For (V protection at elevated temperatures. Recommend V 12. All loading with –2.0 volts. CC 13. V min varies 1:1 with IHCMR EE IHCMR input signal. MC10EP196, MC100EP196 (Note –40 C Min Typ Max Min 3865 3990 ...

Page 7

... Required 500 lfpm air flow when using +5 V power supply. For (V protection at elevated temperatures. Recommend V 19. All loading with –2.0 volts. CC 20. V min varies 1:1 with IHCMR EE IHCMR input signal. MC10EP196, MC100EP196 (Note 14 –40 C Min Typ Max Min 2155 2280 ...

Page 8

... Required 500 lfpm air flow when using +5 V power supply. For (V protection at elevated temperatures. Recommend V 23. All loading with –2.0 volts. CC 24. V min varies 1:1 with IHCMR EE IHCMR input signal. MC10EP196, MC100EP196 –5 –3.0 V (Note 21 –40 C Min Typ Max Min –1145 –1020 – ...

Page 9

... This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than that IN/IN transition. 31. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified propagation delay and transition times. MC10EP196, MC100EP196 = –3 – – ...

Page 10

... –10 3.3 2.97 Figure 5. Propagation Delay versus FTUNE Voltage MC10EP196, MC100EP196 TBD 1000 2000 FREQUENCY (MHz) Figure 4. F /Jitter max capable even under worst case conditions of covering a digital resolution. Typically, the analog input will be driven by an external DAC to provide a digital control with very fine analog output steps ...

Page 11

... A0–A9 address bus), D10 will be asserted to signal the need to cascade the delay to the next EP196 device. When D10 is asserted, the SETMIN pin of MC10EP196, MC100EP196 Figure 6 illustrates the interconnect scheme for cascading two EP196s. As can be seen, this scheme can easily be expanded for larger EP196 chains ...

Page 12

... Figure 8. Cascaded Delay Value of Two EP196s MC10EP196, MC100EP196 TO SELECT MULTIPLEXERS BIT 3 BIT 4 BIT 5 BIT LEN LEN LEN LEN Set Reset Set Reset Set Reset Set Reset INPUT FOR CHIP #1 ...

Page 13

... Device Figure 10. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 – Termination of ECL Logic Devices.) MC10EP196, MC100EP196 Figure 9. One signal channel can be used as reference and the other EP196s can be used to adjust the delay to eliminate the timing skews. Nearly any high–speed system can be fine tuned (as small as 10 ps) to reduce the skew to extremely tight tolerances using the available FTUNE pin ...

Page 14

... AND8001 Odd Number Counters Design – AND8002 Marking and Date Codes – AND8009 ECLinPS Plus Spice I/O Model Kit – AND8020 Termination of ECL Logic Devices – For an updated list of Application Notes, please see our website at http://onsemi.com. MC10EP196, MC100EP196 Levels IH http://onsemi.com 14 ...

Page 15

... MC10EP196, MC100EP196 32–LEAD PLASTIC PACKAGE –T– DETAIL Y 4X –Z– –AB– –AC– DETAIL AD PACKAGE DIMENSIONS LQFP FA SUFFIX CASE 873A–02 ISSUE A –U– DETAIL AD BASE METAL N É É ...

Page 16

... Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800–282–9855 Toll Free USA/Canada MC10EP196, MC100EP196 JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: r14525@onsemi ...

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