mc100ep451fa ON Semiconductor, mc100ep451fa Datasheet - Page 2

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mc100ep451fa

Manufacturer Part Number
mc100ep451fa
Description
3.3v / 5vecl 6-bit Differential Register With Master Reset
Manufacturer
ON Semiconductor
Datasheet

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V
MR
D4
D3
D3
D2
D2
D1
EE
Warning: All V
Supply to guarantee proper operation.
Table 1. PIN DESCRIPTION
* Pins will default LOW when left open.
D [0:5]*, D [0:5]*
MR*
CLK*, CLK*
Q [0:5], Q [0:5]
V
V
EP for QFN−32,
only
CC
EE
25
26
27
28
29
30
31
32
PIN
Figure 1. LQFP−32 Pinout (Top View)
D1
D4
24
1
CC
D0
D5
23
and V
2
D0
D5
22
3
EE
MC100EP451
MC10EP451
pins must be externally connected to Power
ECL Differential Data Inputs
ECL Master Reset Input
ECL Differential Clock Inputs
ECL Differential Data Outputs
Positive Supply
Negative Supply
The Exposed Pad (EP) on the
QFN−32 package bottom is
thermally connected to the die
for improved heat transfer out
of package. The exposed pad
must be attached to a heat−
sinking conduit. The pad is
electrically connected to V
CLK
21
Q5
4
CLK
Q5
FUNCTION
20
5
V
V
19
6
CC
EE
Q0
Q4
18
MC10EP451, MC100EP451
7
Q4
Q0
17
8
EE
16
15
14
13
12
10
11
http://onsemi.com
9
.
2
V
Q3
Q3
V
Q2
Q2
Q1
Q1
CC
CC
CLK
CLK
V
CLK
CLK
Q0
Q0
D1
D0
D0
CC
1
2
3
4
5
6
7
8
MR
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D1
Q1
32
9
Figure 2. QFN−32 Pinout (Top View)
Q1
D2
10
31
Figure 3. Logic Diagram
D2 MR V
Q2
30
11
MC100EP451
MC10EP451
Q2 V
12
29
13
28
EE
CC
D3
Q3
14
27
D
D
D
D
D
D
R
R
R
R
R
R
D3
Q3 V
26
15
Q
Q
Q
Q
Q
Q
V
D4
16
25
EE
CC
24
23
22
21
20
19
18
17
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
D4
D5
D5
Q5
Q5
V
Q4
Q4
EE

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