sy87700v Micrel Semiconductor, sy87700v Datasheet - Page 3

• Manufacturer Part Number: sy87700v
• Description: Sy87700v 5v/3.3v 32-175mbps Anyrate Clock And Data Recovery
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
INPUTS
RDINP, RDINN [Serial Data Input] Differential PECL.
differential receive serial data stream. An internal receive
PLL recovers the embedded clock (RCLK) and data
(RDOUT) information. The incoming data rate can be within
one of five frequency ranges depending on the state of the
FREQSEL pins. See “Frequency Selection” Table.
REFCLK [Reference Clock] TTL Inputs.
frequency synthesizer and the “training” frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN inputs.
CD [Carrier Detect] PECL Input.
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW the
data on the inputs RDIN will be internally forced to a constant
LOW, the data outputs RDOUT will remain LOW, the Link
Fault Indicator output LFIN forced LOW and the clock
recovery PLL forced to look onto the clock frequency
generated from REFCLK.
FREQSEL1, ..., FREQSEL3 [Frequency Select] TTL
Inputs.
shown in the “Frequency Selection” Table.
DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs.
frequency (RCLK/TCLK) and the REFCLK input frequency
as shown in the “Reference Frequency Selection” Table.
CLKSEL [Clock Select] TTL Inputs.
the receiver PLL (CLKSEL = HIGH) or the clock of the
frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs.
M9999-073008
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PIN DESCRIPTIONS
These built-in line receiver inputs are connected to the
This input is used as the reference for the internal
This input controls the recovery function of the Receive
These inputs select the output clock frequency range as
These inputs select the ratio between the output clock
This input is used to select either the recovered clock of
3
OUTPUTS
LFIN [Link Fault Indicator] TTL Output.
RDIN. Active HIGH signal is indicating when the internal
clock recovery PLL has locked onto the incoming data
stream. LFIN will go HIGH if CD is HIGH and RDIN is within
the frequency range of the Receive PLL (1000ppm). LFIN
is an asynchronous output.
RDOUTP, RDOUTN [Receive Data Output] Differential
PECL.
represent the recovered data from the input data stream
(RDIN). This recovered data is specified against the rising
edge of RCLK.
RCLKP, RCLKN [Clock Output] Differential PECL.
represent the recovered clock used to sample the recovered
data (RDOUT).
TCLKP, TCLKN [Clock Output] Differential PECL.
represent either the recovered clock (CLKSEL = HIGH) used
to sample the recovered data (RDOUT) or the transmit clock
of the frequency synthesizer (CLKSEL = LOW).
PLLSP, PLLSN [Clock Synthesis PLL Loop Filter]
PLLRP, PLLRN [Clock Recovery PLL Loop Filter]
POWER & GROUND
V
V
V
GND
N/C
Note 1.
CC
CCA
CCO
This output indicates the status of the input data stream
These ECL 100K outputs (+3.3V or +5V referenced)
These ECL 100K outputs (+3.3V or +5V referenced)
These ECL 100K outputs (+3.3V or +5V referenced)
External loop filter pins for the clock synthesis PLL.
External loop filter pins for the receiver PLL.
V
CC
Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Ground
No Connect
, V
CCA
, V
CCO
must be the same value.
(1)
(1)
(1)
SY87700V