sy89112u Micrel Semiconductor, sy89112u Datasheet - Page 4

• Manufacturer Part Number: sy89112u
• Description: 2.5/3.3v Low Jitter, Low Skew 1 12 Lvpecl Fanout Buffer With 2 1 Input Mux And Internal Termination
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
Pin Description
Truth Table
January 2008
Pin Number
13,22,23,28,
33,34,43
1, 6, 11
42, 41
40, 39
38, 37
36, 35
32, 31
30, 29
27, 26
25, 24
21, 20
19, 18
17, 16
15, 14
7, 10
2, 5
3, 8
44
12
4
9
Note:
1. Transition occurs on next negative transition of the non-inverted input.
Exposed Pad
CLK0, /CLK0
CLK1, /CLK1
EN
VREF-AC0
VREF-AC1
H
H
Q10, /Q10
Q11, /Q11
Pin Name
L
CLK_SEL
VT0, VT1
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
Q9, /Q9
GND,
VCC
EN
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the
device. Inputs accept AC- or DC-coupled differential signals as small as
100mV. Each pin of a pair internally terminates to a VT pin through 50Ω. Note
that these inputs will default to an indeterminate state if left open. Please refer
to the “Input Interface Applications” section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates
to a VT pin. The VT pins provide a center-tap to a termination network for
maximum interface flexibility. See “Input Interface Applications” section for more
details.
Reference Voltage: These outputs bias to V
coupling the inputs (CLK, /CLK). For AC-coupled applications, connect V
to the VT pin and bypass with a 0.01µF low ESR capacitor to V
Interface Applications” section for more details. Maximum sink/source current is
±1.5mA. Due to the limited drive capability, each VREF-AC pin is only intended
to drive its respective VT pin.
This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor
and will default to a logic HIGH state if left open.
This single-ended TTL/CMOS-compatible input functions as a synchronous
output enable. The synchronous enable ensures that enable/disable will only
occur when the outputs are in a logic LOW state. Note that this input is
internally connected to a 25kΩ pull-up resistor and will default to logic HIGH
state (enabled) if left open.
Positive power supply. Bypass with 0.1µF//0.01µF low ESR capacitors and
place as close to each VCC pin as possible.
Differential 100K LVPECL Outputs: These LVPECL outputs are the precision,
low skew copies of the inputs. Please refer to the truth table below for details.
Unused output pairs may be left open. Terminate with 50Ω to V
“LVPECL Output Interface Applications” section for more details.
Ground. GND pins and exposed pad must both be connected to the most
negative potential of chip the ground.
CLK_SEL
H
L
X
4
CLK0
CLK1
L
Q
(1)
[e-mail]
CC
–1.2V. They are used when AC
/CLK0
/CLK1
H
/Q
(1)
CC
or [phone]
M9999-012908-B
CC
. See “Input
–2V. See
SY89112U
REF-AC