sy89464u Micrel Semiconductor, sy89464u Datasheet - Page 4

• Manufacturer Part Number: sy89464u
• Description: Sy89464u Precision Lvpecl Runt Pulse Eliminator 2 1 Mux With 1 10 Fanout And Internal Termination
• Manufacturer: Micrel Semiconductor

Pin Description
Truth Table
December 2007
13, 15, 22, 23, 28
33, 34, 41, 43, 44
Pin Number
1, 6, 11
40, 39
38, 37
36, 35
32, 31
30, 29
27, 26
25, 24
21, 20
19, 18
17, 16
7, 10
2, 5
4, 9
3, 8
42
12
14
Exposed Pad
VREF-AC0
VREF-AC1
Pin Name
VT0, VT1
IN0, /IN0
IN1, /IN1
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
Q9, /Q9
GND,
VCC
CAP
SEL
EN
IN0
X
X
0
1
/IN0
X
X
1
0
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the
device. These inputs accept AC- or DC-coupled signals as small as 100mV
(200mV
Please refer to the “Input Interface Applications” section for more details.
Reference Voltage: These outputs bias to V
coupling inputs IN and /IN. Connect V
Bypass with 0.01µF low ESR capacitor to V
the V
sink/source current is ±1.5mA. Please refer to the “Input Interface Applications”
section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates
to a V
for maximum interface flexibility. Please refer to the “Input Interface Applications”
section for more details.
Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors as close
to the V
Differential Outputs: These differential LVPECL outputs are a logic function of
the IN0, IN1, and SEL inputs. Please refer to the “Truth Table” below for details.
This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25kŸ pull-up resistor
and will default to logic HIGH state if left open. V
Ground: Ground and exposed pad must be connected to the same ground plane.
Power-On Reset (POR) initialization capacitor. When using the multiplexer with
RPE capability, this pin is tied to a capacitor to V
internal RPE logic starts up in a known state. See “Power-On Reset (POR)
Description” section for more details regarding capacitor selection. If this pin is
tied directly to V
function as a normal multiplexer. The CAP pin should never be left open or tied
directly to GND.
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q9
outputs. It is internally connected to a 25kŸ pull-up resistor and will default to a
logic HIGH state if left open. When disabled, CLK output goes LOW and /CLK
goes HIGH. EN being synchronous, outputs will be enabled/disabled when they
are in LOW state. Thus, a runt pulse is avoided if the device is enable/disabled
by an asynchronous control. V
REF-AC
T
Inputs
pin. The V
IN1
pp
CC
X
X
0
1
). Each pin of a pair internally terminates to a V
pins as possible.
pin is only intended to drive its respective V
CC
/IN1
T0
, the RPE function will be disabled and the multiplexer will
X
X
4
1
0
and V
T1
SEL
0
0
1
1
pins provide a center-tap to a termination network
TH
= V
CC
Q
0
1
0
1
REF-AC
Outputs
/2.
[e-mail]
CC
CC
directly to the corresponding V
. Due to the limited drive capability,
/Q
–1.2V. They are used for AC-
1
0
1
0
TH
CC
. The purpose is to ensure the
= V
CC
T
pin. Maximum
T
/2.
pin through 50Ÿ .
M9999-120607-B
or [phone]
T
pin.