sy89229u Micrel Semiconductor, sy89229u Datasheet - Page 3

• Manufacturer Part Number: sy89229u
• Description: Sy89229u 1ghz Precision, Lvds ? 3, ? 5 Clock Divider With Fail-safe Input And Internal Termination
• Manufacturer: Micrel Semiconductor

Pin Description
Truth Table
August 2007
10, 11, 14,15
Pin Number
8, 13
12, 9
1, 4
16
2
3
5
6
7
Exposed Pad
Pin Name
VREF-AC
DIV_SEL
IN, /IN
GND,
Q, /Q
VCC
/MR
NC
EN
VT
DIV_SEL
X
X
0
1
Pin Function
Differential Input: This input pair is the differential signal input to the device,
which accepts AC- or DC-coupled signal as small as 100mV. The input internally
terminates to a VT pin through 50Ÿ and has level shifting resistors of 3.72 kŸ to
VCC. This allows a wide input voltage range from VCC to GND. See Figure 3,
Simplified Differential Input Stage for details. Note that this input will default to a
valid (either HIGH or LOW) state if left open. See “Input Interface Applications”
subsection.
Input Termination Center-Tap: Each side of the differential input pair terminates
to the VT pin. The VT pin provides a center-tap for the input (IN, /IN) to a
termination network for maximum interface flexibility. See “Input Interface
Applications” subsection for more details.
Reference Voltage: This output biases to V
inputs IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01µF
low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is
only intended to drive its respective VT pin. Maximum sink/source current is
±0.5mA. See “Input Interface Applications” subsection.
Single-ended Input: This TTL/CMOS-compatible input disables and enables the
output. It is internally connected to a 25kŸ pull-up resistor and will default to a
logic HIGH state if left open. When disabled, Q goes LOW and /Q goes HIGH.
EN being synchronous, outputs will be enabled/disabled after a rising and a
falling edge of the input clock. V
Single-ended Input: This TTL/CMOS-compatible input, when pulled LOW,
asynchronously sets Q output LOW and /Q output HIGH. Note that this input is
internally connected to a 25kŸ pull-up resistor and will default to logic HIGH
state if left open. V
No Connect
Positive Power Supply: Bypass with 0.1µF in parallel with 0.01µF low ESR
capacitors as close to the V
Differential Output: The output swing is typically 325mV. The output must be
terminated with 100Ÿ across the pair (Q, /Q). See the “Truth Table” below for the
logic function.
Ground: Ground and exposed pad must be connected to a ground plane that is
the same potential as the ground pins.
Single-ended Input: This TTL/CMOS-compatible input selects divide-by-3 when
pulled LOW and divide-by-5 when pulled HIGH. Note that this input is internally
connected to a 25kŸ pull-up resistor and will default to logic HIGH state if left
open. V
Inputs
TH
EN
= V
X
1
1
0
CC
/2.
3
TH
/MR
0
1
1
1
= V
CC
/2.
CC
÷
÷
Q
0
0
pins as possible.
3
5
Outputs
TH
= V
CC
÷
÷
/Q
1
1
3
5
/2.
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CC
–1.2V. It is used for AC-coupling
M9999-080707-A
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