sy89538l Micrel Semiconductor, sy89538l Datasheet
sy89538l
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sy89538l Summary of contents
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... Output enable • 3.3V ±10% power supply (2.5V output capable) • Guaranteed over the industrial temperature range • Available in a 64-pin EPAD-TQFP SY89538L 3.3V, Precision LVPECL and LVDS output dividers, fanout buffers, and clock drivers (XTAL) source – Ideal for reference backup clock source or system test frequency source – ...
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Typical Application Functional Block Diagram January 2008 2 hbwhelp@micrel.com M9999-010808-E or (408) 955-1690 ...
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... Tape and Reel. Pin Configuration January 2008 Operating Package Marking Range Industrial SY89538LHY with Pb-Free bar-line indicator Industrial SY89538LHY with Pb-Free bar-line indicator Commercial SY89538LHZ with Pb-Free bar-line indicator Commercial SY89538LHZ with Pb-Free bar-line indicator = 25°C, DC Electricals only. A 64-Pin EPAD TQFP (H64-1) 3 ...
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Pin Description Power Pin Number Pin Name 1 VCCA VCCD 6, 56 19, 40, 43, 51 VCCO 15 GNDA 16, 30, 31, GND, 47, 55 Exposed Pad Control and Configuration Pin Number Pin Name ...
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Pin Description Control and Configuration (continued) Pin Number Pin Name 24 PEN0 26 PEN1 58 PEN2 60 PEN3 46 SYNC 5 FBSEL 28 PD_4 33 PD_2 35 PD_0 27 PD_5 29 PD_3 34 PD_1 13, 14 PDSEL1, PDSEL0 22 DSEL ...
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... Crystal Oscillator Specification” table. Place crystal as close to the input as possible, keep XTAL and traces away from adjacent noisy traces to minimize noise coupling, and place the XTAL on the same side as the SY89538L (component side). 100K LVPECL Output Drivers. Terminate all LVPECL outputs with 50Ω Each output pair has a respective output frequency control (PSELx, PENx, DSEL). See “ ...
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Output and Frequency Select Tables PSELx Table 3. LVPECL Output Post-Divider and Frequency Select Table LSEL Table 4. LVDS Output Post-Divider and Frequency Select ...
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Absolute Maximum Ratings Supply Voltage ( CCD CCA CCO Input Voltage (RFCK, FBIN)................... –0. XTAL Input Voltage (V ) ......... V XTAL1, 2 Output Current (I ) OUT LVPECL Outputs (Surge) .........................100mA LVPECL Outputs ...
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Reference Clock Inputs/External Feedback Inputs +3.3V ±10%, V CCA CCD CCO Symbol Parameter V Input HIGH Voltage IH V Input LOW Voltage IL V Input Voltage Swing IN V Differential Input Voltage Swing DIFF_IN 100K LVPECL ...
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AC Electrical Characteristics +3.3V ±10%; V CCA CCD CCO (LVPECL) = 50Ω into V –2V; T CCO Symbol Parameter XTAL Input Frequency Range f Reference Input Frequency Range IN Zero Delay Input Frequency Range Phase Detector ...
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Single-Ended and Differential Swings Figure 1a. Single-Ended Voltage Swing January 2008 Figure 1b. Differential Voltage Swing 11 hbwhelp@micrel.com M9999-010808-E or (408) 955-1690 ...
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... Maximum Output Frequency (756MHz Input Mount the crystal as close to the SY89538L as possible to minimize parasitic effects. 2. Mount the crystal on the same plane as the SY89538L to minimize on via hole inductance minimize noise pick up on the loop filter pins, cut the ground plane directly underneath the loop filter component pads and traces ...
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Table 8 summarizes the input reference frequency and associated divider values: f (MHz) RFCK Ref-Div = 1 Ref-Div = 8 73.5 756 65.3 672 58.8 605 53.5 550 49.0 504 … … 14.7 151 14.3 148 14.0 144 13.7 141 ...
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... Zero Delay FBIN Input The SY89538L features a zero delay MUX that forces the output the same phase relationship as the reference. This effectively configures the SY89538L as a zero delay buffer when FBSEL is logic HIGH and the output is fed into the feedback input FBIN as shown in Figures 3a and 3b ...
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Post- Pre- VCO Divider Divider Min. Max. 2.35 3. 2.35 3. 2.35 3. 2.35 3. 2.35 3. 2.35 3. 2.35 3. 2.35 3.02 2 ...
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... PLL input, but potentially more noise from the VCO. Take care to keep the loop filter components on the same side of the board and as close as possible to the SY89538L’s LR and LF pins. To minimize noise pick up on the loop filter pins, cut the ground plane directly underneath the loop filter component pads and traces ...
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Synchronization Output Synchronization Controlled by SYNC Timing Diagram The SYNC control input is used to synchronize all divider outputs of the post divider. When a HIGH-LOW transition is applied to the SYNC control input the outputs are disabled when all ...
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... Detector Freq / Fc Note: 1. Feedback divider = 168 = 42 (6-bit programmable divider) x divide-by-2 x divide-by-2. Reference Frequency = 14, 16, and 18MHz. January 2008 frequencies determined by the loop filter when the SY89538L is driven by a 14MHz to 18MHz crystal when the feedback divider is effectively 168. 3 3.3 3.3 - ...
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... Figure 6 shows the open and closed loop gain of the SY89538L. The closed loop-gain plot shows that the SY89538L when configured with the recommended loop filter values has essentially no jitter peaking near the -3dB point. In addition, the open loop curve shows the frequency at which unity gain occurs for a typical ...
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Input Termination (RFCK and FBIN) Figure 11a. LVPECL Interface (DC-Coupled) Figure 11d. CML Interface (AC-Coupled) Figure 11g. 2.5V CML (DC-Coupled) January 2008 Figure 11b. LVPECL Interface (AC-Coupled) Figure 11e. LVDS (DC-Coupled) Figure 11h. Single-Ended Input Interface 20 Figure 11c. CML ...
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Output Bank and Frequency Control There are five independently programmable output frequency banks, four differential LVPECL output banks and one differential LVDS output bank with three output pairs. Each bank has frequency control DSEL, SELx and Enx to generate different ...
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LVDS LVDS specifies a small swing of 325mV typical nominal 1.2V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common ...
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Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no ...