mpc9893 Integrated Device Technology, mpc9893 Datasheet - Page 11

• Manufacturer Part Number: mpc9893
• Description: 3.3v 1 12 Lvcmos Pll Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ / ICS™ 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9893
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
The variation in cycle time of a signal between adjacent cycles, over a random sample
of adjacent cycle pairs
The pin-to-pin skew is defined as the worst case difference in propagation delay
between any similar delay path within a single device
The time from the PLL controlled edge to the noncontrolled edge, divided by
the time between PLL controlled edges, expressed as a percentage
Figure 12. Output-to-Output Skew t
Figure 14. Output Duty Cycle (DC)
Figure 16. Cycle-to-Cycle Jitter
t
T
P
N
T
T
0
N+1
DC = t
t
SK(O)
P
/T
0
T
x 100%
JIT(CC)
Figure 18. Output Transition Time Test Reference
t
F
= |T
N
SK(O)
–T
N+1
V
V
GND
CC
CC
V
V
GND
V
V
GND
|
CC
CC
CC
CC
÷ 2
÷ 2
÷ 2
11
t
R
The deviation in t
of cycles
CLK0,
CLK1
V
The deviation in cycle time of a signal with respect to the ideal period over a random
sample of cycles
CCLK0, 1
CC
FB
Figure 13. Propagation Delay (t
0.55
=3.3 V
2.4
FB
0
for a controlled edge with respect to a t
V
CC
T
0
=2.5 V
1.8
0.6
Figure 17. Period Jitter
offset) Test Reference
t
(∅)
Figure 15. I/O Jitter
MPC9893
T
T
JIT(∅)
JIT(PER)
(∅)
0
= |T
mean in a random sample
REV. 7 MARCH 3, 2008
, static phase
= |T
0
–T
N
–1/f
1
mean|
0
|
V
V
GND
V
V
GND
CC
CC
CC
CC
÷ 2
÷ 2