mpc93h51 Integrated Device Technology, mpc93h51 Datasheet - Page 8

• Manufacturer Part Number: mpc93h51
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Integrated Device Technology

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC93H51
Low Voltage PLL Clock Driver
8
of an individual capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC93H51 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω, the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to V
thus only a single terminated line can be driven by each
output of the MPC93H51 clock driver. For the series
terminated case, however, there is no DC current draw; thus,
the outputs can drive multiple series terminated lines.
Figure 7
terminated line versus two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC93H51 clock
driver is effectively doubled due to its capability to drive
multiple lines.
MPC93H51
As the noise frequency crosses the series resonant point
The MPC93H51 clock driver was designed to drive high
This technique draws a fairly high level of DC current and
V
CC
illustrates an output driving a single series
Figure 6. V
R
F
22 µF
CC
CCA
÷ 2.
Power Supply Filter
0.01 µF
0.01 µF
V
V
CCA
CC
MPC93H51
8
of an output driving a single line versus two lines. In both
cases, the drive capability of the MPC93H51 output buffer is
more than sufficient to drive 50 Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC93H51. The output
waveform in
step is caused by the impedance mismatch seen looking into
the driver. The parallel combination of the 36 Ω series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
near unity reflection coefficient. It will then increment towards
the quiescent 3.0 V in steps separated by one round trip delay
(in this case 4.0 ns).
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
IN
IN
The waveform plots in
At the load end, the voltage will double to 2.6 V due to the
Since this step is well above the threshold region it will not
Figure 7. Single versus Dual Transmission Lines
MPC93H51
MPC93H51
Output
Output
Buffer
Buffer
10Ω
10Ω
Figure 9
Figure 8
V
Z
R
R
V
L
0
L
S
0
= V
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 14 Ω
= 3.0 (25 ÷ (18 + 17 + 25)
= 1.31 V
should be used. In this case the series
S
shows a step in the waveform. This
(Z
Advanced Clock Drivers Device Data
R
R
R
Figure 8
0
S
S
S
÷ (R
= 36Ω
= 36Ω
= 36Ω
S
+ R
show the simulation results
Freescale Semiconductor
Z
Z
Z
0
O
O
O
+ Z
= 50Ω
= 50Ω
= 50Ω
0
))
OutA
OutB0
OutB1
NETCOM
MPC93H51