mk1491-14 Integrated Device Technology, mk1491-14 Datasheet - Page 2

• Manufacturer Part Number: mk1491-14
• Description: Opti Acpi Firestar Clock Source
• Manufacturer: Integrated Device Technology

MDS 1491-14 B
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126 • [phone]tel • www.icst.com
VDD HOST1-4
Table #4. Power Down Control (IDD measured at 3.3V)
Pin Descriptions
*PCI Function Select (PS) set at Power Up. PS=0, PCI=LOW; PS=1, PCI=ON when clock is switched to “CLK OFF” mode.
Pin Assignment
Key: I = Input, O = Output, P = Power supply connection, I/O = Input on power up, becomes an Output after 10ms.
Internal pull-ups are on pins 5, 16, 18, 19, 21, 22, 24, 25, 27, 28.
VDD
STOP# SLOW#
4, 11, 17, 23
6, 7, 9, 10
1, 20, 26
1
1
0
0
Pin #
EHOST6
14.3(HS)
HOST5-7
HOST1
HOST2
HOST3
HOST4
HOST5
12
13
14
15
16
18
19
21
22
24
25
27
28
2
3
5
8
X14O
GND
VDD
GND
X14I
1
0
0
1
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PLL/OSC OFF
HOST 1, 2, 3, 4
CLK OFF
PCI(SEL1)
EHOST 6
PCIF(LE)
PCI(FS0)
PCI(FS1)
F1(SEL0)
STATE
14.3(HS)
PCI(S/A)
SLOW
HOST 5
HOST7
SLOW#
STOP#
F2(PS)
ON
Name
VDD
X14O
GND
HOST1-4
HOST5-7
X14I
33 MHz
28
27
26
25
24
23
22
21
20
19
18
17
16
15
HOST
LOW
LOW
ON
Type Description
I/O 14.318 MHz output. Amplitude matches VDD. Skew input control for Host 5-7.
I/O PCI Output clock, CPU Frequency Select input, as per Table #2 above. Amplitude = VDD.
I/O PCI Output clock, and Asynchronous PCI Select input, as per Table #2 above.
I/O PCI Output clock, and Frequency Select 1 input, as per Table #1 above.
I/O PCI Output clock that stays enabled when other PCI clocks are low. Low EMI enable input.
I/O PCI output and Frequency Select input. See Table #2 above.
I/O Fixed frequency output and PCI Function Select for "CLK OFF" mode.
I/O Fixed frequency output and frequency SEL0 input per Table #1 above.
STOP#
F1(SEL0)
VDD
F2(PS)
PCI(FS1)
GND
PCIF(LE)
PCI(SEL1)
VDD
PCI(S/A)
PCI(FS0)
GND
SLOW#
HOST7
O
O
O
O
O
P
P
P
P
I
I
I
LOW All outputs asynchronously clamped low. PLLs and 14.3 MHz oscillators are off.
PCI
ON
ON
*
Connect to +3.3V. Must be same voltage on all pins.
Crystal connection. Connect to a 14.31818 MHz crystal or input clock.
Crystal connection. Connect to a 14.31818 MHz crystal, or leave unconnected for clock.
Connect to Ground.
Host Output clocks 1, 2, 3 and 4. Amplitude matches VDD
Connect to VDD supply.
Host Output clock 5. Amplitude matches VDD
Early Host Output clock 6. Amplitude matches VDD
Connect to 2.5 V or 3.3 V. Host 5-7 skew adjusted with HS input. See Table #3 above.
Host Output clock 7. Amplitude matches VDD
Controls clock frequency and power downs, as defined in Table #4 above.
Controls clock frequency and power downs, as defined in Table #4 above.
Table #1. F1, F2 Frequency
Select (MHz)
DESCRIPTION
All Clocks On.
Host Clock smooth frequency transition to and from 33.33 MHz.
Asynchronously clamp HOST5, 7 to GND. HOST1-4,6, PCIF, F1, F2, 14.3M, continue to run.
SEL1
Table #3. Host 5-7 Skew Control
0
0
1
1
VDD
2.5V
3.3V
SEL0
HOST5-7
0
1
0
1
OPTi ACPI Firestar Clock Source
14.318
14.318
24.000
16.934
F1
HS
0
1
2
14.318
48.000
14.318
24.576
F2
Table #2. Host/PCI Frequency Select (MHz)
*2 MHz Accuracy
FS1
0
0
1
1
HOST5-7
HOST5-7
Low EMI for HOST & PCI
FS0
0
1
0
1
HOST5-7
LE
.
.
0
1
HOST
HOST1-4
66.66
60
75
50
.
Low EMI
OFF
ON
PCI (S/A=0)
MK1491-14
33.33*
33.33*
33.33*
33.33*
Revision 061801
PCI (S/A=1)
HOST/2
HOST/2
HOST/2
HOST/2
IDD typ.
50 mA
32 mA
44 mA
1 µA