is61lv10248 Integrated Silicon Solution, Inc., is61lv10248 Datasheet - Page 10

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is61lv10248

Manufacturer Part Number
is61lv10248
Description
1m X 8 High-speed Cmos Static Ram - Integrated Silicon Solution, Inc
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet

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AC WAVEFORMS
WRITE CYCLE NO. 2
IS61LV10248
10
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
2. I/O will assume the High-Z state if OE > V
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
ADDRESS
D
OUT
WE
D
OE
CE
IN
LOW
t
SA
(1,2)
DATA UNDEFINED
(WE Controlled: OE is HIGH During Write Cycle)
IH
.
Integrated Silicon Solution, Inc. — www.issi.com —
VALID ADDRESS
t
t
AW
HZWE
t
t
PWE1
WC
HIGH-Z
t
SD
DATA
IN
VALID
t
HD
t
LZWE
t
HA
CE_WR2.eps
ISSI
1-800-379-4774
04/13/06
Rev. C
®

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