ics2595 Holt Integrated Circuits, Inc., ics2595 Datasheet

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ics2595

Manufacturer Part Number
ics2595
Description
User-programmable Dual High-performance Clock Generator
Manufacturer
Holt Integrated Circuits, Inc.
Datasheet

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Block Diagram
Description
The ICS2595 is a dual-PLL (phase-locked loop) clock
generator specifically designed for high-resolution, high-
refresh rate, video applications. The video PLL generates
any of 16 pre-programmed frequencies through selection
of the address lines FS0-FS3. Similarly, the auxiliary PLL
can generate any one of four pre-programmed frequencies
via the MS0 & MS1 lines.
A unique feature of the ICS2595 is the ability to redefine
frequency selections in both the VCLK and MCLK synthesiz-
ers after power-up. This permits complete set-up of the
frequency table upon system initialization.
User-Programmable Dual High-Performance Clock Generator
ICS2595 RevB 3/2/00
Not recommended for new designs
Applications
Features
PC Graphics
VGA/Supper VGA/XGA Applications
Advanced ICS monolithic phase-locked loop
technology for extremely low jitter
Supports high-resolution graphics - VCLK
output to 145 MHz
Completely integrated - requires only external
crystal (or reference frequency and decoupling)
Power-down modes support portable computing
Sixteen selectable VCLK frequencies
(all user re-programmable)
Four selectable MCLK frequencies
(all user re-programmable)
20-Pin DIP or SOIC
Pin Configuration
ICS2595

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ics2595 Summary of contents

Page 1

... FS0-FS3. Similarly, the auxiliary PLL can generate any one of four pre-programmed frequencies via the MS0 & MS1 lines. A unique feature of the ICS2595 is the ability to redefine frequency selections in both the VCLK and MCLK synthesiz- ers after power-up. This permits complete set-up of the frequency table upon system initialization ...

Page 2

... ICS2595 Pin Descriptions ...

Page 3

... The FS0-FS3 pins and the STROBE pin are used to select the desired operating frequency of the VCLK output from the 16 pre-programmed/user-programmed selections in the ICS2595. These pins are also used to load new frequency data into the registers. The standard interface for the ICS2595 matches the interface of the industry standard ICS2494 ...

Page 4

... ICS2595 LATCHED FS inputs, not the FS inputs themselves, that are interpreted by the internal logic. Interface logic resides between the FS input pins and the programming/frequency select logic. The appropriate "data write" procedure must be observed. See the section "Digital Interface" in this supplement for more information. ...

Page 5

... If a 14.31818 MHz reference is used, the output frequency range would be from 10.697 MHz to 170.486 MHz (but the upper end is first limited to 145 MHz by the ICS2595 output driver). Programming Example Suppose that we want differential CLK output to be 45.723 MHz ...

Page 6

... Power Supply The ICS2595 has three GND pins to reduce the effects of package inductance. All pins are connected to the same potential on the die (the ground bus). All of these pins should connect to the ground plane of the video board as close to the package as is possible ...

Page 7

... ICS2595 ...

Page 8

... ICS2595 AC Characteristics ...

Page 9

... X 0 ICS2595 " " " " ...

Page 10

... ICS2595 All times shown are minimums. Figure 1. ICS2595 Digital Interface Timing ...

Page 11

... ICS2595 ...

Page 12

... ICS2595 Ordering Information ICS2595 Example: ICS XXXX N-SXX Where: “S” denotes strobe option: “XX”denotes default frequencies: 20 PIN DIP Package S=Strobe Option/XX=Default Freq2uencies Package T ype N=DIP (Plastic) M=SOIC Device Type (consists digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device ...

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