ics527-03 Integrated Device Technology, ics527-03 Datasheet - Page 4

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ics527-03

Manufacturer Part Number
ics527-03
Description
Clock Slicer User Configurable Pecl Output Zero Delay Buffer
Manufacturer
Integrated Device Technology
Datasheet
IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB 4
ICS527-03
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB
Typical Example
Note: The series termination resistor is located before
the feedback
VDD
The following connection diagram shows the implementation of the example from the previous section.
This will generate a 50 MHz clock synchronously with a 40 MHz input. The layout diagram below will
produce the waveforms shown on the right.
(PECLIN shown)
50 MHz PECL
50 MHz PECL
40 MHz
0.01 F
R5
R6
DIV2
S0
S1
VDD
FBPECL
GND
CLKIN
PDTS
F0
F1
F2
FBPECL
PECL
PECL
GND
VDD
RES
R4
R3
R2
R1
R0
F6
F5
F4
F3
560
0.01 F
PECL output resistor network is not shown, but
is identical to PECL
VDD
50 MHz
PECL ZDB AND MULTIPLIER/DIVIDER
ICS527-03
REV D 092209

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