ics9ums9001 Integrated Device Technology, ics9ums9001 Datasheet - Page 11

• Manufacturer Part Number: ics9ums9001
• Description: Pc Main Clock - Ck540
• Manufacturer: Integrated Device Technology

IDT
Byte 0 FS Readback, SS Enable, STOP Control Register
Byte 1 LCD Quick Config and CPU Stop ControlRegister
Byte 2 Output Enable and Stop Control Register
Byte 3 Output Enable Register
Byte 4 Output Enable and CLKREQ# Control Register
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ICS9UMS9001
PC MAIN CLOCK - CK540
TM
/ICS
Pin
Pin
Pin
Pin
Pin
-
TM
PC MAIN CLOCK - CK540
CPU_ITP_STOP
LCD_SSC_SEL
PCI_F2_STOP
CPU_ITP_OE
CPU_SS_EN
SRC3_STOP
SRC2_STOP
SRC1_STOP
SRC0_STOP
CPU1_STOP
CPU0_STOP
LCD_SS_EN
LCD_Enable
PCI1_STOP
PCI0_STOP
LCD100_OE
DOT96_OE
PCIF2_OE
CPU1_OE
CPU0_OE
SRC3_OE
SRC2_OE
SRC1_OE
SRC0_OE
SRC3_CR
SRC2_CR
SRC1_CR
SRC0_CR
LCD_CF2
LCD_CF1
LCD_CF0
PCI1_OE
PCI0_OE
Reserved
Reserved
Reserved
REF_OE
USB_OE
Name
Name
Name
Name
Name
FSLC
FSLB
Spread spectrum enable for CPU/SRC/PCI outputs
Free running PCI Stop Control
Output enable for CPU_ITP
Select down or center SSC
Output enable for LCD100
SRC3 CLKREQ3# Enable
SRC2 CLKREQ2# Enable
SRC1 CLKREQ1# Enable
SRC0 CLKREQ0# Enable
Turns on SS for LCD PLL
Output enable for DOT96
CPU Freq. Sel. Bit MSB
PLL3 Quick Config Bit 2
PLL3 Quick Config Bit 1
PLL3 Quick Config Bit 0
CPU Freq. Sel. Bit LSB
Output enable for CPU1
Output enable for CPU0
Output enable for SRC4
Output enable for SRC4
Output enable for SRC4
Output enable for SRC4
Output enable for PCI2
Output enable for PCI1
Output enable for PCI0
CPU_ITP Stop Control
Output enable for USB
Output enable for REF
SRC 3 Stop Control
SRC 2 Stop Control
SRC 1 Stop Control
SRC 0 Stop Control
CPU0 Stop Control
Turns On LCD PLL
CPU1 Stop Control
PCI 0 Stop Control
PCI1 Stop Control
Description
Description
Description
Description
Description
Reserved
Reserved
Reserved
11
Type
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Not controlled by
See Table 2: LCD Quick Configuration
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Free Running
Free Running
Free Running
Down spread
SS Disabled
CLKREQ#
Advance Information
See Frequency Select Table
Off
Off
0
0
0
0
0
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Center spread
CPU_STOP#
Controlled by
PCI_STOP#
PCI_STOP#
SS Enabled
Stops with
Stops with
Stops with
CLKREQ#
Assertion
assertion
assertion
On
On
1
1
1
1
1
1247A—08/28/08
Default
Default
Default
Default
Default
Latch
Latch
1
1
0
0
0
0
0
1
1
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0