ics9ex21501 Integrated Device Technology, ics9ex21501 Datasheet - Page 6

• Manufacturer Part Number: ics9ex21501
• Description: 15 Output Pcie G2/qpi Differential Buffer With 2 1 Input Mux
• Manufacturer: Integrated Device Technology

IDT
TA = T
SMBus Output Low Voltage
1
2
3
4
5
Electrical Characteristics - Input/Supply/Common Parameters
SMBus Input High Voltage
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
Time from deassertion until outputs are >200 mV
DIF_IN input
The differential input clock must be running for the SMBus to be active. Tested at Fin=100MHz.
SMBus Input Low Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
®
Nominal Bus Voltage
SMBus Sink Current
Input SS Modulation
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
Ambient Operating
Input High Voltage
Input Low Voltage
SMBus Operating
Input Frequency
Clk Stabilization
Pin Inductance
PARAMETER
COM
Input Current
OE# Latency
Temperature
Capacitance
Tdrive_PD#
Frequency
Frequency
or T
Trise
Tfall
IND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
SYMBOL
C
f
V
V
t
I
V
V
f
t
MAXSMB
T
LATOE#
PULLUP
T
INDIF_IN
C
t
t
F
MODIN
DRVPD
T
OLSMB
DDSMB
I
F
F
L
RSMB
FSMB
V
V
C
ILSMB
IHSMB
STAB
I
COM
INP
ibyp
OUT
t
t
IND
IN
pin
ipll
ipll
F
R
IH
IL
IN
Single-ended inputs, V
Maximum SMBus operating frequency
Single-ended inputs, except SMBus,
Single-ended inputs, except SMBus,
V
V
clock stabilization or de-assertion of
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
V
From V
IN
V
DD
low threshold and tri-level inputs
low threshold and tri-level inputs
IN
DIF stop after OE# deassertion
DIF_IN differential clock inputs
DD
= 0 V; Inputs with internal pull-up
DIF start after OE# assertion
Logic Inputs, except DIF_IN
= VDD; Inputs with internal pull-
= 3.3 V, 133.33MHz PLL mode
V
Rise time of control inputs
Fall time of control inputs
= 3.3 V, 100MHz PLL mode
DD
Output pin capacitance
(Triangular Modulation)
DIF output enable after
Allowable Frequency
Commmercial range
DD
Single-ended inputs
= 3.3 V, Bypass mode
3V to 5V +/- 10%
PD# de-assertion
PD# to 1st clock
Industrial range
down resistors
Power-Up and after input
CONDITIONS
@ I
resistors
@ V
VDD
PULLUP
OL
6
IN
= GND, V
IN
=
GND - 0.3
-200
MIN
120
-40
1.5
1.5
2.1
2.7
33
80
30
-5
2
4
0
4
100.00
133.33
2.400
0.400
TYP
400
0.5
0.4
2.4
0.3
3.3
25
25
10
0.2
5
V
V
DD
MAX
1000
200
400
110
150
300
DDSMB
300
100
0.8
2.7
0.8
0.4
5.5
33
12
70
85
+ 0.3
5
7
5
6
1
5
5
Datasheet
UNITS NOTES
clocks
MHz
MHz
MHz
kHz
kHz
ms
mA
uA
uA
nH
pF
pF
pF
us
ns
ns
°C
°C
ns
ns
V
V
V
V
V
V
1578—01/18/11
1,4
1,2
1,3
1,3
1,2
1,2
1,5
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1