ics98ulpa877a Integrated Device Technology, ics98ulpa877a Datasheet - Page 6

• Manufacturer Part Number: ics98ulpa877a
• Description: 1.8v Low-power Wide-range Frequency Clock Driver
• Manufacturer: Integrated Device Technology

ICS98ULPA877A
Advance Information
NOTE: The PLL must be able to handle spread spectrum induced skew.
NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters. (Used for low speed system debug.)
NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.
NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset ( t ∅), after power-up.
normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock
of its feedback signal to its reference signal when CK and CK# go to a logic low state, enter the power-down mode
and later return to active operation. CK and CK# may be left floating after they have been driven low for one
complete clock cycle.
1177D—11/9/07
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
Max clock frequency
Application Frequency
Range
Input clock duty cycle
CLK stabilization
Timing Requirements
PARAMETER
SYMBOL
freq
freq
T
d
STAB
tin
App
op
1.8V+0.1V @ 25°C
1.8V+0.1V @ 25°C
CONDITIONS
6
MIN
160
95
40
MAX
410
410
60
15
UNITS
MHz
MHz
µs
%
During