ics9248-20 Integrated Device Technology, ics9248-20 Datasheet - Page 4

• Manufacturer Part Number: ics9248-20
• Description: Pentium/protm System Clock Chip
• Manufacturer: Integrated Device Technology

ICS9248-20 Power Management Requirements
0276D—06/04/07
Power Management
Clock Enable Configuration
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During
power up and power down operations using the PD# select pin will not cause clocks of a shorter or longer pulse than
that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due
to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock
distortion also.
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
ICS9248-20
C
The REF and IOAPIC will be stopped independent of these.
C
P
P
P
C
U
I S
U
_ I
_
_
P
G
X
S
0
0
S
1
1
D
S
N
T
T
#
A
T
O
O
O
L
P
P
P
#
#
#
P
C
0
I S
_ I
0
0
P (
1
1
O
G
1
S
X
(
(
0
0
o
1
1
E (
E (
p
N
D
D
T
w
(
r e
A
s i
s i
N
O
n
n
r e
L
t a
a
a
a
a
r o
P
b
b
b
b
S
o i
D
#
m
e l
e l
e l
e l
T
o
) n
l a
A
) d
) d
) d
) d
w
T
3
2
1
2
1
) n
E
P
4
W
R
_
N
0
1
1
1
1
D
. o
W
o
u r
N
r f
#
n
s i
n
L
n i
n i
2
a
g
3
g
m
e t
1
1
m
C
1
1
1
1
e
0
0
P
a
n
d
0
0
s
P
C
y c
x
L
L
L
g
6 /
6 /
U
H
H
C I
o
o
o
e
6
6
C
z
z
w
w
w
s
L
6 .
6 .
L
o
K
K
M
M
f f
4
-
-
e r
e
3
3
P
3
3
C
3 .
3 .
L
L
L
C I
o
o
o
M
M
w
w
w
L
H
H
K
z
z
R
O
E
h t
4
4
F
S
R
R
R
R
8
8
r e
I ,
o t
u
u
u
u
M
M
O
n
n
n
n
p
C
n
n
n
n
H
H
A
p
o l
n i
n i
n i
n i
e
z
P
z
g
g
g
g
k c
d
C I
0
1
, s
, s
R
R
R
R
C
u
u
u
u
y r
O
n
n
n
n
t s
n
n
n
n
f f
n i
n i
n i
n i
l a
g
g
g
g
R
R
R
R
V
u
u
u
u
O
C
n
n
n
n
n
n
n
n
O
f f
n i
n i
n i
n i
s
g
g
g
g