ics9248-87 Integrated Device Technology, ics9248-87 Datasheet - Page 2

• Manufacturer Part Number: ics9248-87
• Description: Frequency Generator & Integrated Buffers For Celeron & Pii/iii
• Manufacturer: Integrated Device Technology

Preliminary Product Preview
General Description
Pin Configuration
Third party brands and names are the property of their respective owners.
ICS9248-87
2, 6, 16, 24, 27, 34,
5, 9, 13, 20, 26, 30,
32, 33, 35, 36, 37,
19, 18, 17, 15, 14
PIN NUMBER
39, 40, 41
21, 22
44, 45
8, 7
42
10
11
12
23
25
28
29
31
43
46
47
48
38
1
3
4
2
CPUCLK [1:0]
PCICLK [7:3]
SDRAM [7:0]
VDDLAPIC
PIN NAME
SEL24_48#
GNDLCPU
VDDLCPU
24_48MHz
SDRAM_F
3V66 [1:0]
PCICLK0
PCICLK1
PCICLK2
SDATA
IOAPIC
48MHz
SCLK
REF1
VDD
GND
PD#
FS3
FS0
FS1
FS2
X1
X2
2
TYPE
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
14.318 MHz reference clock.
Frequency select pin.
3.3V Power supply for SDRAM output buffers, PCI output buffers, reference
output buffers and 48MHz output
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Ground pin for 3V outputs.
3V66 clock outputs.
Frequency select pin.
PCI clock output.
Frequency select pin.
PCI clock output.
Frequency select pin.
PCI clock output.
PCI clock outputs.
48MHz output clocks
Sel pin for enabling 24MHz or 48MHz
H=24MHz L=48MHz
Clock output for super I/O/USB
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
SDRAM clock output - free running not affected by I
SDRAM clock outputs
Ground pin for the CPU clocks.
CPU clock outputs.
Power pin for the CPUCLKs. 2.5V
2.5V clock output
Power pin for the IOAPIC. 2.5V
Power Groups
DESCRIPTION
2
C