ics9248-199 Integrated Device Technology, ics9248-199 Datasheet - Page 2

• Manufacturer Part Number: ics9248-199
• Description: Frequency Generator For Sis 735/740 With Amd K7 Processor
• Manufacturer: Integrated Device Technology

ICS9248-199
0376E—12/23/02
Pin Configuration
1, 11, 17, 21, 25,
PIN NUMBER
24, 26, 34, 39,
4, 5, 8, 14, 20,
16, 15, 13
41, 45, 48
19, 18
37, 38
42, 46
36
10
12
22
23
27
28
29
30
31
32
33
35
40
43
44
47
2
3
6
7
9
SDRAM_STOP#
AGPCLK (1:0)
PCICLK (4:2)
CPU_STOP#
AGP_STOP#
PCI_STOP#
CPUCLKC0
CPUCLKT0
24_48MHz
PIN NAME
PCICLK_F
PCICLK0
PCICLK1
CPUCLK
AGPSEL
SDRAM
SDATA
IOAPIC
48MHz
SCLK
VDDL
REF0
REF1
VDD
GND
PD#
FS0
FS1
FS2
FS3
FS4
NC
X1
X2
TYPE
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
-
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output.
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Ground pin for outputs.
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
PCI clock output, not affected by PCI_STOP#.
Frequency select pin.
PCI clock output.
Frequency select pin.
PCI clock output.
PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
48MHz output clock.
AGP frequency select pin.
Clock output for super I/O/USB default is 24MHz.
Clock pin of I
Data pin for I
Stops all AGP clocks besides the AGP_F clocks at logic 0 level,
when input low.
Stops all SDRAM clocks at logic 0 level, when input low
(when MODE active).
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms.
Stops all CPUCLKs clocks at logic 0 level, when input low.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low.
SDRAM clock output.
No connect pins.
CPU clock output.
Supply for CPU and IOAPIC clocks at 2.5V nominal.
Complementary clocks of differential pair CPU outputs. This clock is
180° out of phase with SDRAM clocks. These open drain outputs
need an external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. This clock is in phase
with SDRAM clocks. This open drain output needs an external 1.5V
pull-up.
2.5V clock output.
2
2
2
C circuitry 5V tolerant.
C circuitry 5V tolerant.
DESCRIPTION