ics9248-105 Integrated Device Technology, ics9248-105 Datasheet - Page 2

• Manufacturer Part Number: ics9248-105
• Description: Frequency Generator & Integrated Buffers For Celeron
• Manufacturer: Integrated Device Technology

Preliminary Product Preview
General Description
Pin Configuration
Third party brands and names are the property of their respective owners.
ICS9248-105
17, 16, 15, 13, 12
PIN NUMBER
2, 9, 10, 18, 26,
5, 6, 14, 23, 28,
30, 31, 32, 34,
35, 36, 38, 39,
42, 33, 41
29, 37
8, 7
40,
11
19
20
21
22
24
25
27
43
44
45
46
47
48
1
3
4
PCICLK [4:0]
CPU_STOP#
AGP_STOP#
SDRAM[8:0]
VDDLAPIC
PIN NAME
PCI_STOP#
48_24MHz
CPUCLK_F
VDDLCPU
PCICLK_F
SDRAM12
SDRAM11
SDRAM10
CPUCLK0
AGP [1:0]
SDRAM9
SDATA
IOAPIC
MODE
SCLK
REF1
REF0
VDD
GND
PD#
FS1
FS0
FS2
X1
X2
2
TYPE
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Frequency select pin.
14.318 MHz reference clock.
3.3V Power supply for SDRAM, AGP, PCI, reference output buffers and
48MHz output
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Ground pin for 3V outputs.
AGP outputs defined as 2X PCI.
Frequency select pin.
Free running PCI clock not affected by PCI_STOP# .
PCI clock outputs.
Stops all CPUCLKs [1:0] besides the CPUCLK_F clocks at logic 0 level,
when input low
SDRAM clock output
Stops all PCICLKs [5:1] besides the CPUCLK_F clocks at logic 0 level,
when input low
SDRAM clock output
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
SDRAM clock output
Stops all AGP clocks [0:1] at logic 0 level, when input low
SDRAM clock output
Clock input of I2C input, 5V tolerant input
Data input for I2C serial input, 5V tolerant input
Function select pin, 1=Desktop Mode, 0=Mobile Mode.
Selectable 48 or 24MHz output, default is 48MHz
SDRAM clock outputs
CPU clock output
Free running CPU clock. Not affected by the CPU_STOP#.
Supply for CPU clocks, either 2.5V or 3.3V nominal
2.5V clock output
Power pin for the IOAPIC outputs. 2.5V.
Frequency select pin.
14.318 MHz reference clock.
2
DESCRIPTION