ics86953i-147 Integrated Device Technology, ics86953i-147 Datasheet - Page 6

• Manufacturer Part Number: ics86953i-147
• Description: Low Skew, 1-to-9 Ics86953i-147 Differential-to-lvcmos / Lvttl Zero Delay Buffer
• Manufacturer: Integrated Device Technology

As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS86953I-147
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin. Fig-
ure 1 illustrates this for a generic V
requires that an additional10Ω resistor along with a 10µF bypass
capacitor be connected to the V
W
Figure 2 shows how a differential input can be wired to accept
single ended levels. The reference voltage V
by the bias resistors R1 and R2. The bypass capacitor (C1) is
used to help filter noise on the DC bias. This bias circuit should be
located as close to the input pin as possible. The ratio of R1 and
R2 might need to be adjusted to position the V
the input voltage swing. For example, if the input clock swing is
2.5V and V
V
ended swing and V
requires that the sum of the output impedance of the driver (Ro)
and the series resistance (Rs) equals the transmission line
impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
ICS86953I-147
P
ICS86953BYI-147 REVISION B FEBRUARY 26, 2010
REF
OWER
IRING THE
at 1.25V. The values below are for when both the single-
S
UPPLY
DD
D
= 3.3V, R1 and R2 value should be adjusted to set
IFFERENTIAL
F
DD
ILTERING
are at the same voltage. This configuration
T
I
NPUT TO
ECHNIQUES
DDA
DD
pin.
pin and also shows that V
F
IGURE
A
REF
CCEPT
DDA
A
2. S
= V
and V
REF
PPLICATION
DD
INGLE
in the center of
S
/2 is generated
DDO
INGLE
E
should be
NDED
E
NDED
S
DDA
IGNAL
6
I
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
L
NFORMATION
impedance. For most 50 applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading
for slower and weaker LVCMOS driver. When using single ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V
than -0.3V and V
the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
D
EVELS
RIVING
D
IFFERENTIAL
F
IGURE
IH
cannot be more than V
1. P
V
V
I
NPUT
DDO
DDA
OWER
.01µF
.01µF
S
©2010 Integrated Device Technology, Inc.
UPPLY
3.3V
10Ω
10µF
F
DD
ILTERING
+ 0.3V. Though some of
IL
cannot be less