ics87952i-147 Integrated Device Technology, ics87952i-147 Datasheet - Page 7

• Manufacturer Part Number: ics87952i-147
• Description: Low Skew, 1-to-11 Lvcmos/lvttl Clock Multiplier/zero Delay Buffer
• Manufacturer: Integrated Device Technology

ICS87952I-147 Data Sheet
ICS87952AYI-147 REVISION C AUGUST 4, 2009
L
The schematic of the ICS87952I-147 layout example is shown in
Figure 2A. This layout example is used as a general guideline.
The layout in the actual system will depend on the selected com-
AYOUT
Logic Input Pin Examples
VDD
VDD
RU1
1K
RD1
Not Install
G
Driv er_LVCMOS
UIDELINE
Q1
Set Logic
Input to
'1'
To Logic
Input
pins
F
IGURE
Ro ~ 7 Ohm
2A. ICS87952I-147 LVCMOS/LVTTL C
R3
VDD
43
RU2
Not Install
RD2
1K
Set Logic
Input to
'0'
To Logic
Input
pins
Zo = 50
VDD
F_SELC
F_SELB
F_SELA
10 - 15
10u
R7
C16
VDD
R4
1K
0.01u
C11
ICS87952
1
2
3
4
5
6
7
8
U1
VCO_SEL
F_SELC
F_SELB
F_SELA
MR/nOE
REF_CLK
GNDI
FB_IN
LOCK
R5
1K
LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
7
ponent types, the density of the components, the density of the
traces, and the stack up of the P.C. board.
M
ULTIPLIER
0.1u
C1
(U1-16)
/Z
GNDO
GNDO
VDDO
VDDO
VDD=3.3V
0.1uF
C2
ERO
QB1
QB0
QA4
QA3
VDDO
VDD
R1
D
24
23
22
21
20
19
18
17
ELAY
43
R2
B
UFFER
(U1-20)
43
Zo = 50
0.1uF
S
C3
©2009 Integrated Device Technology, Inc.
CHEMATIC
Zo = 50
(U1-21)
0.1uF
C4
E
XAMPLE
(U1-25)
Receiv er
Receiv er
0.1uF
C5
(U1-32)
0.1uF
C6