ad7011 Analog Devices, Inc., ad7011 Datasheet - Page 10

• Manufacturer Part Number: ad7011
• Description: Cmos, Adc P/4 Dqpsk Baseband Transmit Port
• Manufacturer: Analog Devices, Inc.

As Figure 12 illustrates, the ramp-down envelope reaches zero
after three symbols, hence the fourth symbol does not actually
get transmitted.
Reconstruction Filters
The reconstruction filters smooth the DAC output signals,
providing continuous time I and Q waveforms at the output
pins. These are 4th order Bessel low-pass filters with a –3 dB
frequency of approximately 25 kHz. The filters are designed to
have a linear phase response in the passband and due to the
reconstruction filters being on-chip, the phase mismatch
between the I and Q transmit channels is kept to a minimum.
Transmit Section Digital Interface
MODE1 = MODE2 = DGND: Digital /4 DQPSK Mode
Figures 4 and 5 shows the timing diagrams for the transmit
interface when operating in TIA /4 DQPSK mode. POWER is
sampled on the rising edge of MCLK. When POWER is
brought high, the transmit section is brought out of sleep mode
and initiates a self-calibration routine as described above. Once
the self-calibration is complete, the READY signal goes high to
indicate that a transmit burst can now begin. BIN (Burst in) is
brought high to initiate a transmit burst and should only be
brought high if the READY signal is already high.
When BIN goes high, the READY signal goes low on the next
rising edge of MCLK and TxCLK becomes active after a
further three MCLK cycles. TxCLK can be used to clock out
the transmit data from the ASIC or DSP on the rising edge of
TxCLK and the AD7011 will latch TxDATA on the falling
edge of TxCLK.
When BIN is brought low, the AD7011 will continue to clock in
the current Di-bit symbol (X
further 8 TxCLK cycles (four symbols). After the final TxCLK,
READY goes high waiting for BIN to be brought high to begin
the next transmit burst.
AD7011
PHASE MAX
(QTx–QTx)
(ITx–ITx),
SYMBOL
TxDATA
EFFECT
TxCLK
BOUT
BIN
X
1
Y
1
N + 4
, Y
X
N
N + 4
Y
N
) and will continue for a
X
N+1
0
0
= 480
Y
t
N+1
1
X
N+2
0
0
Figure 12. Transmit Burst
RAMP-UP ENVELOPE
Y
N+2
3 SYMBOL
X
N+3
0
0
–10–
Y
N+3
When POWER is brought low this puts the transmit section into
a low power sleep mode, drawing minimal current. The analog
outputs go high impedance while in low power sleep mode.
MODE1 = V
Figure 6 shows the timing diagram for the transmit interface
when operating in analog mode. In this mode the /4 DQPSK
modulator is bypassed and direct access to the I and Q 10-bit
DACs is provided. Loading of the I and Q DACs is accom-
plished using a 4 wire 16-bit serial interface. The pins TxCLK,
TxDATA and BIN are all reconfigured as inputs, with the
functions of FRAME, IDATA and QDATA respectively.
I and Q data are loaded via the IDATA and QDATA pins and
FRAME synchronizes the loading of the 16-bit I and Q words.
FRAME should be brought high one clock cycle prior to the I
and Q MSBs. Data is latched on the rising edge of MCLK,
MSB first, where only the first 10 data bits are significant. Con-
tinuous updating of the I and Q DACs is required at a rate of
MCLK/16.
MODE1 = DGND; MODE2 = V
A special FTEST (Frequency TEST) mode is provided for the
customer, where no phase modulation takes place and the mod-
ulator outputs remain static. ITx is set to zero and QTx is set to
full scale as Figure 7 illustrates. However, the normal ramp-up/
down envelope is still applied during the beginning and end of a
burst.
MODE1 = MODE2 = V
This mode is reserved for factory test only and should not be
used by the customer for correct device operation.
X
N+4
Q
I
1
1
Y
N+4
X
N+5
DD
Y
N+5
; MODE2 = DGND: Analog Mode
RAMP-DOWN ENVELOPE
X
N+6
Q
I
N
N
Y
3 SYMBOL
DD
N+6
: Factory Test Mode
X
Q
I
N+7
N+1
N+1
Y
DD
N+7
: Frequency Test Mode
X
Q
I
N+8
N+2
N+2
Y
N+8
Q
I
N+3
N+3
Q
I
N+4
REV. B
N+4