ad73422 Analog Devices, Inc., ad73422 Datasheet - Page 26

• Manufacturer Part Number: ad73422
• Description: Dual Low Power Cmos Analog Front End With Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

AD73422
Reset
The RESET signal initiates a master reset of the AD73422. The
RESET signal must be asserted during the power-up sequence
to assure proper initialization. RESET during initial power-up
must be held long enough to allow the internal clock to stabilize.
If RESET is activated any time after power-up, the clock con-
tinues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this power-
up sequence the RESET signal should be held low. On any
subsequent resets, the RESET signal must meet the minimum
pulsewidth specification, t
The RESET input contains some hysteresis; however, if an
RC circuit is used to generate the RESET signal, an external
Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from on-
chip program memory location 0x0000 once boot loading com-
pletes.
MODES OF OPERATION
Table XXI summarizes the AD73422 memory modes.
MODE C
0
0
1
1
NOTES
1
2
3
4
5
All mode pins are recognized while RESET is active (low).
When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.
When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.
When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.
Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
2
MODE B
0
1
0
0
3
RSP
MODE A
0
0
0
1
.
4
space. Program execution is held off until all 32 words have been loaded. Chip is configured
in Full Memory Mode.
0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does
not automatically use or wait for these operations.
space. Program execution is held off until all 32 words have been loaded. Chip is config-
ured in Host Mode. (REQUIRES ADDITIONAL HARDWARE.)
until internal program memory location 0 is written to. Chip is configured in Host Mode.
Booting Method
BDMA feature is used to load the first 32 program memory words from the byte memory
No Automatic boot operations occur. Program execution starts at external memory location
BDMA feature is used to load the first 32 program memory words from the byte memory
IDMA feature is used to load any internal memory as desired. Program execution is held off
Table XXI. Modes of Operations
DD
is ap-
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Setting Memory Mode
Memory Mode selection for the AD73422 is made during chip
reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
Passive configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as
a programmable flag output without undue strain on the
processor’s output driver. For minimum power consumption
during power-down, reconfigure PF2 to be an input, as the pull-
up or pull-down will hold the pin in a known state and will not
switch.
Active configuration involves the use of a three-statable exter-
nal driver connected to the Mode C pin. A driver’s output en-
able should be connected to the DSP’s RESET signal such that
it only drives the PF2 pin when RESET is active (low). When
RESET is deasserted, the driver should three-state, thus allow-
ing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
level and not oscillate should the three-state driver’s level hover
around the logic switching point.
1
REV. 0
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