ad73460 Analog Devices, Inc., ad73460 Datasheet - Page 27

• Manufacturer Part Number: ad73460
• Description: Six-input Channel Analog Front End
• Manufacturer: Analog Devices, Inc.

The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the BMS bit.
Boot Memory Select (BMS) Disable
The AD73460 also allows the user to boot the processor from
one external memory space while using a different external
memory space for BDMA transfers during normal operation.
CMS can be used to select the first external memory space for
BDMA transfers and BMS to select the second external memory
space for booting. The BMS signal can be disabled by setting
Bit 3 of the System Control Register to 1. The System Control
Register is illustrated in Figure 15.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Regis-
ter is shown in Figure 16. The byte memory space consists of
256 pages, each of which is 16K × 8.
The byte memory space on the AD73460 supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32-megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
Byte Memory DMA (BDMA, Full Memory Mode)
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally, and steals only one
DSP cycle per 8-, 16-, or 24-bit word transferred.
REV. A
SPORT0 ENABLE
SPORT1 ENABLE
SPORT1 CONFIGURE
1 = ENABLED
0 = DISABLED
1 = ENABLED
0 = DISABLED
1 = SERIAL PORT
0 = FI, FO, IRQ0,
15 14 13 12 11 10 9
0
IRQ1, SCLK
15 14 13 12 11 10 9
0
0
0
0
BMPAGE
0
Figure 15. System Control Register
0
Figure 16. BDMA Control Register
0
0
SYSTEM CONTROL REGISTER
0
0
BDMA CONTROL
1
0
0
8
0
8
0
7
0
7
0
6
0
6
0
5
0
5
0
4
0
4
0
3
1
3
0
2
0
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
2
1
BTYPE
1
0
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
1
1
0
0
PWAIT
PROGRAM MEMORY
WAIT STATES
BMS ENABLE
0
1
0 = ENABLED
1 = DISABLED
DM (0x3FE3)
DM (0x3FFF)
–27–
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table XXII shows the data formats sup-
ported by the BDMA circuit.
BTYPE
00
01
10
11
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally, the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer, so it can be
used to check the status of the transfers. When it reaches zero,
the transfers have finished and a BDMA interrupt is generated.
The BMPAGE and BEAD registers must not be accessed by the
DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to create
a destination word, it is transferred to or from on-chip memory.
The transfer takes one DSP cycle. DSP accesses to external
memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether or not
the processor is held off while the BDMA accesses are occur-
ring. Setting the BCR bit to 0 allows the processor to continue
operations. Setting the BCR bit to 1 causes the processor to
stop execution while the BDMA accesses are occurring, to clear
the context of the processor and start execution at address 0
when the BDMA accesses have completed.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and the AD73460. The port is used to
access the on-chip program memory and data memory of the
Internal
Memory Space
Program Memory
Data Memory
Data Memory
Data Memory
Table XXII. Data Formats
Word Size
24
16
8
8
AD73460
Alignment
Full Word
Full Word
MSBs
LSBs